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參數(shù)資料
| 型號： | ST7597 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | AC97 Audio Codec(AC97 音頻編解碼器) |
| 中文描述： | AC97音頻編解碼器（AC97音頻編解碼器） |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 208K |
| 代理商： | ST7597 |
2.1.2 - AC-link Audio Input Frame
(SDATA_IN)
The audio input frame data streams correspond to
the multiplexed bundles of all digital input data
targeting the ST7597 controller. As is the case for
audio output frame, each AC-link audio input frame
consists of 12 20-bit time slots. Slot 0 is a special
reserved time slot containing 16 bits which are used
for AC-link protocol infrastructure.
Within slot 0 the first bit is a global bit (SDATA_IN
slot0, bit 15) which flags is in the ST7597 is in the
"Codec Ready" state or not. If the "Codec Ready"
bit is a 0, this indicates that the ST7597 is not
ready for normal operation. This condition is nor-
mal following the deassertion of power on reset for
example, while ST7597’s voltage reference settle.
When the AC-link "Codec Ready" indicator bit is a
1 it indicates that the AC-link and the ST7597
control and status registers are in fully operational
state. The ST7597 controller must futher probe the
Powerdown Control/Status Register (section 6.3)
to determinate exactly which subsections, if any,
are ready.
Prior to any attempts at putting ST7597 into opera-
tion the ST7597 controller should poll the first bit in
the audio input frame (SDATA_IN slot 0, bit 15) for
an indication that the ST7597 has gone "Codec
Figure 5 :
AC-link Audio Input Frame
Ready". Once ST7597 is sampled "Codec Ready"
then the next 12-bit positions sampled by the
ST7597 controller indicate which of the corre-
sponding 12 time slots are assigned to input data
streams, and that they contain valid data.
The Figure 5 illustrates the time slot based AC-link
protocol.
A new audio input frame begins with a low to high
transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately fol-
lowing falling edge of BIT_CLK, ST7597 samples
the assertion of SYNC. This falling edge marks the
time when both sides of AC-link are aware of a new
audio frame. On the next rising edge of BIT_CLK,
ST7597 transitionss SDATA_IN into the first bit
position of slot 0 (Codec Ready Bit). Each new bit
position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by ST7597
controller on the following falling edge of
BIT_CLK. This sequence ensures that data tran-
sitions, and subsequent sample points for both
incoming and outgoing data streams are time
aligned (see Figure 6).
SDATA_IN’s composite stream is MSB justified
(MSB first) with all non-valid slots’bit positions
stuffed with 0’s by the ST7597.
FUNCTIONAL DESCRIPTION
(continued)
SYNC
BITCLK
SDATAIN
Tag Phase
Data Phase
20.8
m
s (48kHz)
12.288MHz
81.4ns
7
SYNC
BITCLK
SDATAIN
End of previous
Audio Frame
Slot 2
Valid
Frame
Slot 1
ST7597 samples first
SDATA_IN bit of frame here
ST7597 samples SYNC here
7
Figure 6 :
Start of an Audio Input Frame
ST7597
9/20
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| ST75C176BD | 功能描述:緩沖器和線路驅(qū)動器 Low Power Transcvr RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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