參數(shù)資料
型號(hào)： ST7597
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： AC97 Audio Codec(AC97 音頻編解碼器)
中文描述： AC97音頻編解碼器（AC97音頻編解碼器）
文件頁(yè)數(shù)： 10/20頁(yè)
文件大小： 208K
代理商： ST7597
2.1.2.1 - Slot 1 :
Status Address Port
The status port is used to monitor status for ST7597
functions including, but not limited to, mixer set-
tings, and power management (refer to the control
register section 6.3 of this specification).
Audio input frame slot 1’s stream echoes the control
register index, for historical reference, for the data
to be returned in slot 2. (Assuming that slots1 and 2
has been tagged "valid" by ST7597 during slot 0).
Status Address Port bit assignments :
Bit(19)
Reserved (stuffed with 0)
Bit(18:12) Control register index (Echo of the
register index for which data is being
returned)
Bit(11:0)
Reserved (stuffed with 0’s)
The first bit (MSB) generated by ST7597 is always
stuffed with a 0. The following 7 bit positions com-
municate the associated control register address,
and the trailing 12-bit positions are stuffed with 0’s
by ST7597.
2.1.2.2 - Slot 2 :
Status Data Port
The status data port delivers 16-bit control register
read data.
Bit(19:4)
Control register read data (stuffed with
0’s if tagged "invalid" by ST7597)
Bit(3:0)
Reserved (stuffed with 0’s)
If slot 2 is tagged "invalid" by ST7597, then the
entire slot will be stuffed with 0’s by ST7597.
2.1.2.3 - Slot 3 :
PCM Record Left Channel
Audio input frame slot 3 is the left channel output
of ST7597 input MUX, post-ADC.
ST7597’s ADCs is a 16-bit resolution one in this
version.
ST7597 out its ADC output data (MSB first), and
stuffs any trailing non-valid bit positions with 0’s
(Bit(3:0)).
Figure 7 :
AC-link Powerdown Timing
2.1.2.4 - Slot 4 :
PCM Record Right Channel
Audio input frame slot 4 is the right channel output
of ST7597 input MUX, post-ADC.
ST7597’s ADCs is a 16-bit resolution one in this
version.
ST7597 out its ADC output data (MSB first), and
stuffs any trailing non-valid bit positions with 0’s
(Bit(3:0)).
2.1.2.5 - Slots 5-12 :
Reserved
Audio input frame slots 5-12 are reserved for future
use and are always stuffed with 0’s by the ST7597.
2.2 - AC-link Low Power Mode
The AC-link signals can be placed in a low power
mode (see section 3.3). When ST7597’s general
purpose register (20h) is programmed to the appro-
priate value, both BIT_CLK and SDATA_IN will be
brought to, and held at a logic low voltage level
(see Figure 7).
BIT_CLK and SDATA_IN are transitioned low im-
mediately (within the maximum specified time) fol-
lowing the decode of the write to the general
purpose register (20h) with PR4. When the ST7597
controller driver is at the point where it is ready to
program the AC-link into its low power mode, slots
1 and 2 are assumed to be the only valid stream in
the audio output frame (at this point in time it is
assumed that all sources of audio input have also
been neutralized).
The ST7597 controller should also drive SYNC,
and SDATA_OUT low after programming ST7597
to this low power, "halted" mode.
Once the ST7597 has been instructed to halt
BIT_CLK, a special "wake-up" protocol must be
used to bring the AC-link to the active mode since
normal audio output and input frames can not be
communicated in the absence of the BIT_CLK.
FUNCTIONAL DESCRIPTION
(continued)
SYNC
BIT_CLK
BIT_CLK not to scale
SDATA_OUT
SDATA_IN
Data PR4
TAG
Write to 0x20
Slot12
Prev. Frame
TAG
Slot12
Prev. Frame
7
ST7597
10/20
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PDF描述
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