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參數(shù)資料
| 型號(hào)： | ST7597 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | AC97 Audio Codec(AC97 音頻編解碼器) |
| 中文描述： | AC97音頻編解碼器（AC97音頻編解碼器） |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | ST7597 |
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FUNCTIONAL DESCRIPTION
1 - System Usage
1.1 - ST7597 Connection to the digital controller
ST7597 communicates with its companion ST7597
controller via a digital serial link, "AC-link". All digital
audio streams, and command/status information
are communicated over this point to point serial
interconnect. A breakout of signals connecting the
two is shown below. The section 2 gives a detailed
description of the AC-link.
1.2 - Clocking
ST7597 derives its clock internally from an externally
attached 24.576MHz crystal and drives a buffered
and divided down (1/2) clock to its digital companion
controller over AC-link under the signal name
"BITCLK". Clock jitter at the DACs and ADCs is a
fundamental impediment to high quality output, and
the internally generated clock provides ST7597 with
a clean clock that is independant of the physical
proximity of the ST7597 companion digital controller
(henceforth referred to as the "ST7597 controller).
The beginning of all audio sample packets, or "Audio
Frames", transferred over the AC-link is synchro-
nized to the rising edge of the "SYNC" signal. SYNC
is driven by the ST7597 controller. The ST7597
controller takes BITCLK as an input and generates
SYNC by dividing BITCLK by 256 and applying
some conditioning to tailor its duty cycle. This yields
a 48kHz SYNC signal whose period defines an
audio frame. Data is transitioned on AC-link on every
rising edge of BITCLK, and subsequently sampled
on the receiving side of the AC-link on each imme-
diately following falling edge of BITCLK.
1.3 - Resetting the ST7597
There are 3 types of ST7597 reset :
1.
A "cold" reset where all ST7597 logic (registers
included) is initialized to its default state ;
2.
A "warm" reset where the contents of the
ST7597 register set are left unaltered ;
3.
A "register" reset which only initializes the
ST7597 registers to their default states.
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET
AC-LINK
D
C
S
7
Figure 1
After signaling a reset to the ST7597, the ST7597
controller should not attempt to play or capture audio
data until it has sampled a "Codec Ready" indication
from ST7597 (refer to section 2 for details).
2 - Digital Interface
2.1 - AC-link Digital Serial Interface Protocol
ST7597 incorporates a 5-pin digital serial interface that
links it to the ST7597 controller. AC-link is a bidirec-
tional, fixed rate, serial PCM digital stream. It handles
multiple input, and output audio streams, as well as
control registers accesses employing a time division
multiplexed (TDM) scheme. The AC-link architecture
divides each audio frame into 12 outgoing and 12
incoming data streams, each with 20-bit sample reso-
lution. With the headroom that the AC-link architecture
provides, the current version of ST7597 including DAC
and ADC resolution of 16-bits, will be increased to 18
or 20 bits DAC/ADC resolution.
The data streams defined by the ST7597 include :
- PCM PLAYBACK data (2 output slots)
2 channel composite PCM output stream
- PCM RECORD data (2 input slots)
2 channel composite PCM input stream
- Control (2 output slots)
Control register write port
- Status (2 input slots)
Control register read port
Synchronization of all AC-link data transactions is
signaled by the ST7597 controller. ST7597 drives
the serial bit clock onto AC-link, which the ST7597
controller then qualifies with a synchronization sig-
nal to construct audio frames.
SYNC, fixed at 48kHz, is derived by dividing down
the serial bit clock (BITCLK). BITCLK, fixed at
12.288MHz, provides the necessary cloking granu-
larity to support 12, 20-bit outgoing and incoming
time slots AC-link serial data is transitioned on each
rising edge of BITCLK. The receiver of AC-link data,
ST7597 for outgoing data and ST7597 controller
for incoming data, samples each serial bit on the
falling edges of BITCLK.
The AC-link protocol provides for a special 16-bit
(13-bit defined, with 3 reserved trailing bit positions)
time slot (slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current
audio frame. A "1" in a given bit position of slot 0
indicates that the corresponding time slot within the
current audio frame has been assigned to a data
stream, and contains valid data. If a slot is "tagged"
invalid, it is the responsability of the source of the
data (ST7597 for the input stream, ST7597 control-
ler for the output stream), to stuff all bit positions
with 0’s during that slot’s active time.
ST7597
6/20
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