參數(shù)資料
型號： ST7597
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： AC97 Audio Codec(AC97 音頻編解碼器)
中文描述： AC97音頻編解碼器（AC97音頻編解碼器）
文件頁數(shù)： 7/20頁
文件大?。?/td> 208K
代理商： ST7597
SYNC remains high for a total duration of 16 BITCLK
at the beginning of each audio frame. The portion of
the audio frame where SYNC is high is defined as
the "Tag Phase". The remainder of the audio frame
where SYNC is low is defined as the "Data Phase".
Additionally, for power saving, all clock, sync, and data
signals can be halted. For that the ST7597 is imple-
mented as a static design to allow its register contents
to remain intact when entering a power saving mode.
2.1.1 - AC-link Audio Output Frame
(SDATAOUT)
The audio output frame data streams correspond to
the multiplexed bundles of all digital output data target-
ing the ST7597’s DAC inputs, and control registers. As
briefly mentioned earlier, each audio output frame
supports up to 12 20-bit outgoing data time slots. Slot
0 is a special reserved time slot containing 16 bits which
are used for AC-link protocol infrastructure.
Within slot 0 the first bit is a global bit (SDATAOUT
slot0, bit 15) which flags the validity for the entire
audio frame. If the "Valid Frame" bit is a 1, this
indicates that the current audio frame contains at
least one slot time of valid data. The next 12-bit
positions sampled by ST7597 indicate which of the
corresponding 12 time slots contain valid data. In
this way data streams of differing sample rates can
be transmitted across AC-link at its fixed 48kHz
audio frame rate. The Figure 3 illustrates the time
slot based AC-link protocol.
A new audio output frame begins with a low to high
transition of SYNC. SYNC is synchronous to
the rising edge of BITCLK. On the immediately
Figure 2 :
Standard Bi-directional Audio Frame
following falling edge of BITCLK, ST7597 samples
the assertion of SYNC. This falling edge marks the
time when both sides of AC-link are aware of a new
audio frame. On the next rising edge of BITCLK,
the ST7597 controller transitions SDATAOUT into
the first bit position of slot 0 (Valid Frame Bit).
Each new bit position is presented to AC-link on
a rising edge of BITCLK, and subsequently sam-
pled by ST7597 on the following falling edge of
BITCLK. This sequence ensures that data transi-
tions, and subsequent sample points for both in-
coming and outgoing data streams are time aligned
(see Figure 4).
SDATAOUT’s composite stream is MSB justified
(MSB first) with all non-valid slots’bit positions
stuffed with 0’s by the ST7597 controller.
In the event that there are less than 20 valid bits
within an assigned and valid time slot, the ST7597
controller always stuffs all trailing non-valid bit po-
sitions of the 20-bit slot with 0’s.
As an example, consider an 8-bit sample stream
that is being played out to one of the ST7597’s
DACs. The first 8-bit positions are presented to the
DAC (MSB justified) followed by the next 12-bit
positions which are stuffed with 0’s by the ST7597
contoller. This ensures that regardless of the reso-
lution of the implemented DAC, no DC biasing will
be introduced by the least significant bits.
When mono audio sample streams are output from
the ST7597 controller it is necessary that both left
and right sample stream time slots be filled with the
same data.
FUNCTIONAL DESCRIPTION
(continued)
Slot
SYNC
Outgoing Streams
Incoming Streams
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PCM
RIGHT
PCM
RIGHT
PCM
LEFT
PCM
LEFT
CMD
DATA
STATUS
DATA
STATUS
ADR
CMD
ADR
TAG
TAG
1
2
3
4
5
6
7
8
9
10
11
12
Tag Phase
Data Phase
7
SYNC
BITCLK
SDATAOUT
Tag Phase
Data Phase
20.8
m
s (48kHz)
12.288MHz
81.4ns
7
Figure 3 :
AC-link Audio Output Frame
ST7597
7/20
相關(guān)PDF資料
PDF描述
ST75C185 LOW POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS
ST75C185BD LOW POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS
ST75C185BDR MOSFET, P, SOIC; Current, Id cont:9.8A; Case style:SOIC; Base number:4463; Charge, gate p channel:37nC; Pins, No. of:8; Resistance, Rds on @ Vgs = 10V:0.011R; Resistance, Rds on @ Vgs = 2.5V:0.02R; Resistance, Rds on @ Vgs = RoHS Compliant: Yes
ST75C185BN LOW POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS
ST75C185BTR LOW POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS
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ST75C176BD 功能描述:緩沖器和線路驅(qū)動器 Low Power Transcvr RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
ST75C176BDR 功能描述:緩沖器和線路驅(qū)動器 Low Power Transcvr RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
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