參數(shù)資料
型號： ST72P621L4B1
英文描述： LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS. FLASH OR ROM MEMORY. LVD. WDG. 10-BIT ADC. 2 TIMERS. SCI. SPI
中文描述： 低速USB 8端點與3位微控制器。 FLASH或ROM存儲器。內(nèi)徑。水分散粒劑。 10位ADC。 2定時器。脊髓損傷。的SPI
文件頁數(shù)： 85/133頁
文件大?。?/td> 1864K
代理商： ST72P621L4B1
ST7262
55/133
10.4 SERIAL PERIPHERAL INTERFACE (SPI)
10.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.4.2 Main Features
s
Full duplex synchronous transfers (on 3 lines)
s
Simplex synchronous transfers (on 2 lines)
s
Master or slave operation
s
Six master mode frequencies (fCPU/4 max.)
s
fCPU/2 max. slave mode frequency
s
SS Management by software or hardware
s
Programmable clock polarity and phase
s
End of transfer interrupt flag
s
Write collision, Master Mode Fault and Overrun
flags
10.4.3 General Description
Figure 39 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
–SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
Figure 39. Serial Peripheral Interface Block Diagram
SPIDR
Read Buffer
8-Bit Shift Register
Write
Read
Data/Address Bus
SPI
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
STATE
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
0
7
0
7
SPIF WCOL
MODF
0
OVR
SSI
SSM
SOD
bit
SS
1
0
相關(guān)PDF資料
PDF描述
ST72T213G1B3 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
ST72T213G1B6 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
ST72T213G1M3 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
ST72T213G1M6 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
ST72T213 REAL-TIME DEVELOPMENT TOOLS FOR THE ST7 MCU FAMILY
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