參數(shù)資料
型號(hào)： ST72P621L4B1
英文描述： LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS. FLASH OR ROM MEMORY. LVD. WDG. 10-BIT ADC. 2 TIMERS. SCI. SPI
中文描述： 低速USB 8端點(diǎn)與3位微控制器。 FLASH或ROM存儲(chǔ)器。內(nèi)徑。水分散粒劑。 10位ADC。 2定時(shí)器。脊髓損傷。的SPI
文件頁數(shù)： 14/133頁
文件大?。?/td> 1864K
代理商： ST72P621L4B1
ST7262
110/133
EMC CHARACTERISTICS (Cont’d)
12.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 64 and Figure 65 for standard
pins and in Figure 66 and Figure 67 for true open
drain pins.
Standard Pin Protection
To protect the output structure the following ele-
ments are added:
– A diode to VDD (3a) and a diode from VSS (3b)
– A protection device between VDD and VSS (4)
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to VDD (2a) and a diode from VSS (2b)
– A protection device between VDD and VSS (4)
Figure 64. Positive Stress on a Standard Pad vs. VSS
Figure 65. Negative Stress on a Standard Pad vs. VDD
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
Path to avoid
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
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