參數(shù)資料
型號(hào): ST72F60E1M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件頁數(shù): 17/139頁
文件大?。?/td> 1993K
代理商: ST72F60E1M1
ST7260xx
Electrical characteristics
113/139
16.3.2
Operating conditions with low voltage detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA. Refer to Figure 9 on page 26.
16.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
Table 59.
Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+
Low Voltage Reset Threshold
(VDD rising)
VDD Max. Variation
50 V/ms
3.4
3.7
4.0
V
VIT-
Low Voltage Reset Threshold
(VDD falling)
VDD Max. Variation
50 V/ms
3.2
3.5
3.8
V
Vhyst
Hysteresis (VIT+ - VIT-)
(1)
1.
Guaranteed by characterization - not tested in production
100
175
220
mV
VtPOR
VDD rise time rate
(2)
2.
The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested
in production.
0.5
50
V/m
s
Table 60.
Supply current consumption
Symbol
Parameter
Conditions
Typ
Max
Unit
ΔI
DD(
ΔTa)
Supply current variation vs.
temperature
Constant VDD and fCPU
10 (1)
%
IDD
CPU RUN mode
I/Os in input mode
fCPU = 4 MHz
7.5
9 (2)(1)
mA
fCPU = 8 MHz
10.5
13 (2)
CPU WAIT mode
fCPU = 4 MHz
6
8 (1)
mA
fCPU = 8 MHz
8.5
11 (2)
CPU HALT mode (3)
LVD disabled
25
40 (1)
μA
USB Suspend mode (4)
LVD disabled
100
120
μA
LVD enabled
230
1.
Not tested in production, guaranteed by characterization.
2.
Oscillator and watchdog running. All others peripherals disabled.
3.
USB Transceiver is powered down.
4.
CPU in Halt mode. Current consumption of external pull-up (1.5 Kohms to USBVCC) and pull-down (15 Kohms to
VSSA) not included.
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