參數(shù)資料
型號: ST72F60E1M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件頁數(shù): 137/139頁
文件大小: 1993K
代理商: ST72F60E1M1
ST7260xx
USB interface (USB)
97/139
These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this
endpoint, so the software has the time to elaborate the received data before acknowledging
a new transaction.
Bits 3:0 = EA[3:0] Endpoint address.
Software must write in this field the 4-bit address used to identify the transactions directed to
this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”.
14.4.10
Endpoint 0 register B (EP0RB)
This register is used for controlling data reception on Endpoint 0. It is also reset by the USB
bus reset.
Bit 7 = Forced by hardware to 1.
Bits 6:4 = Refer to the EPnRB register for a description of these bits.
Bits 3:0 = Forced by hardware to 0.
14.5
Programming considerations
The interaction between the USB interface and the application program is described below.
Apart from system reset, action is always initiated by the USB interface, driven by one of the
USB events associated with the Interrupt Status Register (ISTR) bits.
14.5.1
Initializing the registers
At system reset, the software must initialize all registers to enable the USB interface to
properly generate interrupts and DMA requests.
Table 45.
STAT_RX bits
STAT_RX1
STAT_RX0
Meaning
00
DISABLED: reception transfers cannot be
executed.
01
STALL: the endpoint is stalled and all reception
requests result in a STALL handshake.
10
NAK: the endpoint is naked and all reception
requests result in a NAK handshake.
11
VALID: this endpoint is enabled for reception.
EP0RB
Reset value:
1000 0000 (80h)
76
543
21
0
1
DTOG
RX
STAT
RX1
STAT
RX0
00
R/W
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