參數(shù)資料
型號: ST72F60E1M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件頁數(shù): 134/139頁
文件大小: 1993K
代理商: ST72F60E1M1
USB interface (USB)
ST7260xx
94/139
14.4.6
Control register (CTLR)
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate delay.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-chip voltage regulator that supplies the
external pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note:
After turning on the voltage regulator, software should allow at least 3 s for stabilisation of
the power supply before using the USB interface.
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing
at least 600 ns before issuing the HALT instruction.
0: Suspend mode inactive
1: Suspend mode active
When the hardware detects USB activity, it resets this bit (it can also be reset by software).
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the USB interface, just as if a RESET sequence
came from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software clears this bit, at which point a “USB-RESET”
interrupt will be generated if enabled.
CTLR
Reset value:
0000 0110 (06h)
76
543
21
0
00
RESUME
PDWN
FSUSP
FRES
R/W
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