參數(shù)資料
型號(hào)： ST72E85A5G0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封裝： WINDOWED, CERAMIC, QFP- 80
文件頁(yè)數(shù)： 79/117頁(yè)
文件大?。?/td> 748K
代理商： ST72E85A5G0
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ST7285C
4.6 A/D CONVERTER (ADC)
4.6.1 Introduction
The on-chip Analog to Digital Converter peripheral
is a single 8-bit successive approximation ratio-
metric monotonic ADC, to which up to 8 different
analog voltages (depending on device specifica-
tion as illustrated in Block Diagram) may be ap-
plied from external sources. The result of the con-
version is stored in the 8-bit Data Register. The A/
D converter is controlled through the ADC Control/
Status Register.
4.6.2 Functional Description
The A/D converter is enabled by setting the A/D
Converter ON bit (ADON) in the ADC Control/Sta-
tus Register. A delay time is then required for the
converter to stabilize (typically 10
s, see Electrical
Characteristics)).
When the A/D function is enabled, the associated
pins (see MCU Block Diagram) may be used as
analog inputs. The inputs must first be enabled for
analog input by setting the corresponding bit(s) of
the relevant Port Configuration Register as de-
scribed in the Section on I/O Ports. Bits CH2 to
CH0 of the A/D Converter Control/Status Register
may then be coded to select the channel to be
converted. Using a pin, or pins, as analog inputs
does not affect the ability to read the port as logic
inputs.
The A/D converter may be disabled by resetting
the ADON bit. This feature allows the reduction of
power consumption when no conversion is in
progress. The A/D converter is disabled after Pow-
er-On and external resets.
When enabled, the A/D converter performs a con-
tinuous conversion of the selected channel. When
a conversion is completed (16
s for f
CPU =4
MHz), the result is loaded into the read only Result
Data Register and the COCO (Conversion Com-
plete) flag is set. No interrupt is generated. Any
write to the A/D Converter Control/Status Register
aborts the current conversion, resets the COCO
flag and starts a new conversion.
The A/D converter is ratiometric. An input voltage
equal to, or greater than VDD , converts to FFh (full
scale) without overflow indication if greater. An in-
put voltage equal to, or lower than VSS converts to
00h. The conversion is monotonic: the results nev-
er decrease if the analog input does not and never
increase if the analog input does not.
The 8-bit conversion is accurate to within 2 LSB.
The minimal conversion time is 32 ADC clock cy-
cles (16
s if A/D clock frequency at 2 MHz). The
A/D converter clock is generated from the CPU
clock divided by 2.
The high and low level reference voltages are con-
nected to VDD and VSS. Conversion accuracy may
therefore be degraded by voltage drops and noise
in the event of heavily loaded or badly decoupled
power supply lines.
The A/D converter is not affected by WAIT mode
but, in power sensitive applications, it can be disa-
bled before entering this mode. When the MCU
enters HALT mode with the A/D converter ena-
bled, the A/D clocks are stopped and the converter
is disabled until the HALT mode is exited and the
start-up delay has elapsed. A stabilisation time is
also required before accurate conversions can be
performed.
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