- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98145 > ST72E85A5G0 (STMICROELECTRONICS) 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 PDF資料下載
參數(shù)資料
| 型號(hào)： | ST72E85A5G0 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 |
| 封裝： | WINDOWED, CERAMIC, QFP- 80 |
| 文件頁(yè)數(shù)： | 39/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST72E85A5G0 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
28/117
ST7285C
4.2 SERIAL COMMUNICATIONS INTERFACE
4.2.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of Baud rates thanks to the
presence of two Baud rate generator systems: the
first is of conventional type and yields common
communications Baud rates with standard oscilla-
tor frequencies; the second features a program-
mable prescaler capable of dividing the input fre-
quency by any factor from 1 to 255, thus offering a
very wide range of Baud rates even with non-
standard oscillator frequencies. Transmitter and
Receiver circuits are independent and can operate
at different Baud rates; indeed, each can select ei-
ther type of Baud rate generator. External connec-
tions are by means of two I/O pins: TDO (Port
PB0) for the Transmit Data output and RDI (Port
PB1) for the Receive Data input.
4.2.2 Features
– Full duplex, asynchronous communications
– NRZ standard format (Mark/Space)
– Dual Baud rate generator systems
– Independently programmable transmission and
reception Baud rates
– Separate Transmit and Receive Baud rates
– Programmable word length (8 or 9 bits)
– Receive buffer full, Transmit buffer empty and
End of Transmission flags
– Receiver wake-up function by the most signifi-
cant bit or by idle line
– Muting function for multiprocessor configurations
– Separate enable bits for Transmitter and Receiver
– Noise, Overrun and Frame Error detection
– Four interrupt sources with flags
– Overall accuracy better than 1% of Baud rate.
4.2.3 Serial Data Format
Serial data is transmitted and received as frames
comprising the following elements:
– An Idle Line in the ”high” state prior to transmis-
sion or reception.
– A Start bit in the ”low” state, denoting the start of
each character.
– Character data word (8 or 9 bits), least significant
bit first.
– A Stop bit in the ”high” state, indicating that the
frame is complete.
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCCR1 con-
trol register.
An Idle Line condition is interpreted on receiving
an entire frame of ”ones”.
A Break is interpreted on receiving ”zeros” for
some multiple of the frame period.
4.2.4 Data Reception and Transmission
The following description is best read with refer-
ence to the SCI Block Diagram illustrated in Figure
1, where it will be noted that the SCDR data regis-
ter is shown as two separate registers, one for
transmitted data and the other for received data.
The Serial Communications Data Register (SCDR)
performs a dual function (Read And Write), since it
accesses two separate registers, one for transmis-
sion (TDR) and one for reception (RDR). The TDR
register provides the data interface between the in-
ternal bus and the output shift register for data to be
transmitted, while the RDR register provides an in-
terface between the input shift register and the in-
ternal bus for incoming data.
When the SCDR is read, the RDR is accessed and
its contents are transferred to the data bus. The
RDRF (RDR Full Flag) in the SCSR register is set
to ”1” as soon as the word in the receiver shift reg-
ister is transferred to the RDR register.
When the SCDR is written to, the data word is
transferred to the TDR register. The TDRE flag
(TDR empty) in the SCSR register is set to ”1” as
soon as the word in the TDR is transferred to the
transmit shift register.
Incoming data is received in a serial shift register
and then transferred to a parallel Receive Data
Register (RDR) as a complete word, thus allowing
the next incoming character to be received in the
shift register while the current character is still in
the RDR.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
4.2.5 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overheads
for all non addressed receivers. Communications
protocols in such configurations generally issue
the recipient address as a message header.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72F321J9T7 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321J7T3 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321J7T1 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321J9T5 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F324BJ6B6 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72F260G1B5 | 功能描述:8位微控制器 -MCU Flask 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F260G1M6 | 功能描述:8位微控制器 -MCU Flash 4K SPI/I2C/SCI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F260G1M6/TR | 功能描述:8位微控制器 -MCU 8B MCU FLASH OR ROM MEMORY RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F262G1B5 | 功能描述:8位微控制器 -MCU Flask 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72F262G1B6 | 功能描述:8位微控制器 -MCU 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。