參數(shù)資料
型號： ST72E85A5G0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封裝： WINDOWED, CERAMIC, QFP- 80
文件頁數(shù)： 38/117頁
文件大小： 748K
代理商： ST72E85A5G0
27/117
ST7285C
I/O PORTS (Cont’d)
4.1.3 I/O Port Implementation
On the ST7285C, the pull down is always absent,
the pull up exists only where an interrupt facility is
present (Ports C4, C5, D4, D5, F0, F1, F2, F3,
G3). On port A, the analog inputs are directly con-
trolled by the ADC.The I/O port register configura-
tions are reduced to the following.
4.1.3.1 Ports A0-A7, B0-B7, C0-C3, C6, C7, D0-
D3, D6, D7,E0-E7, F4-F7, G0-G2, G4-G7, H0-H5
These ports do not offer interrupt capabilities.
Note: Open drain I/O is implemented on I2C pins
(pins 19 and 20) and high voltage pins (PH3/4/5).
The design uses special I/O devices without P
channel, thus forbidding the push pull configura-
tion.
In this case there is neither pull up register nor op-
tion register. These registers do not exist and so
cannot be read or written to.
4.1.3.2 Ports C4, C5, D4, D5, F0-F3, G3
These ports offer interrupt capabilities.
In this case there is no pull up register since the
pull-up is present only when the interrupt feature is
selected. This register does not exist and so can-
not be read or written to.
Switching these I/O ports from one state to anoth-
er should be done in such a sequence as to pre-
vent unwanted side effects. Recommended safe
transitions are illustrated in Figure 14. Other tran-
sitions are potentially risky and should be avoided,
since they are likely to present unwanted side-ef-
fects such as spurious interrupt generation.
Figure 14. Recommended I/O State Transition Diagram
DDR
MODE
OPTION
0
input
no pull-up, no pull-down, no interrupt
1
output
push-pull (or open drain: see note)
DDR
OR
MOD
E
OPTION
0
input
no pull-up, no pull-down,
no interrupt
0
1
input
interrupt, pull-up
1
0
output
open-drain, no pull-up
1
output
push-pull, no pull-up,
no pull-down
11
00
01
Interrupt
pull-up
push-pull
no pull-up
open-drain
no pull-up
no pull-down
INPUT
OUTPUT
10
no pull-up
no interrupt
INPUT
no pull-down
(Reset state)
XX
= DDR, OR
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