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參數(shù)資料
| 型號： | ST72E85A5G0 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80 |
| 封裝： | WINDOWED, CERAMIC, QFP- 80 |
| 文件頁數(shù)： | 51/117頁 |
| 文件大?。?/td> | 748K |
| 代理商： | ST72E85A5G0 |
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ST7285C
16-BIT TIMER (Cont’d)
4.3.4 Input Capture
The timer features two input capture registers and
an input capture interrupt enable bit.
The Input Capture Registers (ICR1 and ICR2)
each consist of two 8-bit registers: the most signif-
icant byte registers (ICHR1 and ICHR2), and the
least significant byte registers (ICLR1 and ICLR2).
In the following description, the variable
i may rep-
resent 1 or 2.
ICR
i is a read-only registers used to latch the val-
ue of the free running counter after a defined tran-
sition is sensed by the input capture edge detector
at pin ICAP
i. This transition is software program-
mable through the IEDG
i bit of the Timer Control
Register (TCR
i). When IEDGi is set, a rising edge
triggers the capture; when IEDG
i is low, the cap-
ture is triggered by a falling edge.
When an input capture occurs, the ICF
i flag in the
Timer Status Register (TSR) is set. An interrupt is
requested if the interrupt enable bit, ICIE, of TCR1
is set, provided the I bit of the CCR is reset. Other-
wise, the interrupt remains pending until both con-
ditions become true. It is cleared by reading the
TSR followed by a read or write of the LSB of ICR
i.
The result stored in ICR
i is one more than the val-
ue of the free running counter on the rising edge of
the internal processor clock preceding the active
transition on the ICAP
i pin (see Figure 5). This de-
lay is required for internal synchronization. There-
fore, the timing resolution of the input capture sys-
tem is one count of the free running counter, i.e. 2,
4 or 8 internal clock cycles, depending on the clock
control bits of TCR2.
The free running counter is transferred to ICR
i on
each proper signal transition regardless of wheth-
er the Input Capture Flag ICF
i is set or cleared.
The ICR
i always contains the free running counter
value which corresponds to the most recent input
capture.
After reading the MSB of ICRi, transfer of input
capture data is inhibited until the LSB is also read.
This implies that the minimum pulse period is de-
termined by the time required to respond to the in-
terrupt and to execute the service routine.
Reading ICLR
i does not inhibit transfer of counter
data. The minimum pulse period is determined by
the time required to read the least significant byte
and to perform necessary actions. There is no
conflict between reading ICR
i and the running
counter transfer, since they occur on opposite
clock edges as shown in Figure 5.
ICR
i is undetermined on power-on, and is not af-
fected by an external Reset. Hardware circuitry
must provide protection against generating an un-
desired input capture when changing the edge
sensitivity option of the ICAP
i pin by programming
the IEDG
i bit.
During HALT mode, if at least one valid input cap-
ture edge occurs on the ICAP
i pin, the input cap-
ture detection circuitry is armed. This does not set
any timer flags, and does not ”wake-up” the MCU.
If the MCU is awoken by an interrupt, the input
capture flag will be active, and data corresponding
to the first valid edge during HALT mode will be
present. If HALT mode is exited by a Reset, the in-
put capture detection circuitry is reset and thus,
any active edge that occurred during HALT mode
will be lost.
Figure 21. Input Capture Timing Diagram
FF01
FF02
FF03
CPU CLOCK
÷2
CPU CLOCK
÷4
CPU CLOCK
÷8
INTERNAL CLOCK T10
INTERNAL CLOCK T11
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
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