參數(shù)資料
型號： ST7285C
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口
文件頁數(shù)： 7/117頁
文件大小： 748K
代理商： ST7285C
7/117
ST7285C
Pin
Pin Name(s)
Basic Function
Ground for Output Buff-
ers
Power Supply for Out-
put Buffers
Oscillator Output pin.
Oscillator Input pin.
Alternate Function
Remarks
1
V
SSP
-
This pin is connected to pin 41
2
V
DDP
This pin is connected to pin 42
3
4
OSCOUT
OSCIN
5
PC0/MISO_B
I/O Port PC0
SPI B master in/slave
out data input/output
SPI B Master Out/
Slave In Data Input/
Output
SPI B Serial Clock
SPI B Slave Select
Output Compare 2
on Timer B
Output Compare 1
on Timer B
Input Capture 2
on Timer B
Input Capture 1
on Timer B.
SPI A Master In/Slave
Out Data Input/Output
SPI A Master Out/
Slave In data Input/
Output
SPI A Serial Clock
SPI A Slave Select
-
Alternate function or I/O. The I/O configuration
is software selectable as triggered input or
push pull output.
6
PC1/MOSI_B
I/O Port PC1
7
8
PC2/SCK_B
PC3/SS_B
I/O Port PC2
I/O Port PC3
9
PC4/OC2_B
I/O Port PC4
Alternate function or I/O. Software selectable
as triggered input, push pull output, or trig-
gered interrupt input with pull up (Interrupt I10).
10
PC5/OC1_B
I/O Port PC5
11
PC6/IC2_B
I/O Port PC6
Alternate function or I/O. The I/O configuration
is software selectable as triggered input or
push pull output.
12
PC7/IC1_B
I/O Port PC7
13
PD0/MISO_A
I/O Port PD0
14
PD1/MOSI_A
I/O Port PD1
15
16
17
PD2/SCK_A
PD3/SS_A
PD4
I/O Port PD2
I/O Port PD3
I/O Port PD4
Software selectable as triggered input, push
pull output, open drain output or triggered in-
terrupt input with pull up (Interrupt I9).
Alternate function or I/O. The I/O configuration
is software selectable as triggered input or
open drain output.
Bidirectional. An active low signal forces MCU
initialization. This event is the top priority non-
maskable interrupt. As an output, it can be
used to reset external peripherals.
Input. This pin MUST be tied directly to V
SS
during normal operation.
18
PD5
I/O Port PD5
-
19
PD6/SCL
I/O Port PD6
I
2
C Serial Clock
20
PD7/SDA
I/O Port PD7
I
2
C Serial Data
21
RESET
General Reset
-
22
TEST
RESERVED
-
23
V
DD
Power Supply forall log-
ic circuitry
Ground for all logic cir-
cuitry
I/O Port PE0
I/O Port PE1
I/O Port PE2
I/O Port PE3
I/O Port PE4
I/O Port PE5
I/O Port PE6
I/O Port PE7
-
Except for output buffers and pull-ups.
24
V
SS
-
25
26
27
28
29
30
31
32
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
-
-
-
-
-
-
-
Software selectable as triggered input or push
pull output.
-
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