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| 型號(hào)： | ST7285C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 40/117頁(yè) |
| 文件大小： | 748K |
| 代理商： | ST7285C |
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ST7285C
16-BIT TIMER
(Cont’d)
4.3.5 Output Compare
Two output compare registers are present: Output
Compare Register 1 and Output Compare Regis-
ter 2 (OCR1 and OCR2). These registers can be
used for several purposes, such as controlling an
output waveform or indicating when a period of
time has elapsed. The OCMPi pin is associated
with the Output Comparei function (i = 1 or 2).
The Output Compare Registers are unique in that
all bits are readable and writable and are not af-
fected by the timer hardware or by Reset. Ifa com-
pare function is not used, the two bytes of the cor-
responding Output Compare Registers can be
used as general purpose storage locations.
4.3.5.1 Output Compare Registers
The Output Compare Registeri (OCRi) is a 16-bit
register, which is made up of two 8-bit registers:
the most significant byte register (OCHRi) and the
least significant byte register (OCLRi).
In this section, the index,i may be 1 or 2.
The content of OCRi is compared with the content
of the free running counter once during every timer
clock cycles, i.e. once every 8, 4 or 2 internal proc-
essor clock periods or 2 external clock periods ac-
cording to the clock control bits of the Timer Con-
trol Register (TCR2). If match is found, the Output
Compare Flag OCFiof the TSR is set and the Out-
put Level bit (OLVLi) of the TCR1 is clocked to the
OCMPi pin (see output compare timing diagrams
Figure 6, Figure 7, Figure 8). OLVLi is copied to
the corresponding output level latch and hence, to
the OCMPi pin regardless of whether the Output
Compare Flag (OCFi) is set or not. The value in
the OCRiand the OLVLi bit should be changed af-
ter each successful comparison in order to control
an output waveform or establish a new elapsed
timeout.
An interrupt accompanies a successful output
compare if the corresponding interrupt enable bit
OCIE of the TCR1 is set, provided the I-bit of the
CCR is cleared. Otherwise, the interrupt remains
pending until both conditions are true. It is cleared
by a read ofTSR followed by an access to the LSB
of the OCRi.
After a processor write cycle to the OCHR regis-
ter, the output compare function is inhibited until
the OCLRi is also written. Thus, the user must
write both bytes if the MSB is written first. A write
made to only the LSB will not inhibit the compare
function. The minimum time between two succes-
sive edges on the OCMPi pin is a function of the
software program and the clock control bits of the
TCR2.
The OCMPi output latch is forced low during reset
and stays low until valid compares change it to a
high level. Because the OCFi flag and the OCRi
are undeterminate at power-on and are not affect-
ed by an external reset, care must be exercise
when initiating the output compare function with
software. The following procedure is recommend-
ed to prevent the OCFi flag from being set be-
tween the time it is read and the write to OCR:
– Write to OCHRi(further compares are inhibited).
– Read the TSR (first step of the clearance of OC-
Fi which may be already set).
– Write to OCLRi (enables the output compare
function and clears OCFi).
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