參數(shù)資料
型號: ST62E35B
廠商: 意法半導體
英文描述: 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
中文描述: 8位檢察官辦公室/存儲器與阿微控制器/ D轉(zhuǎn)換器,16位自動重加載定時器,EEPROM中,SPI和UART
文件頁數(shù): 47/82頁
文件大?。?/td> 617K
代理商: ST62E35B
47/82
ST62T35B/E35B
TIMINGS MEASUREMENT MODES
(Cont’d)
CP2 triggered restart mode with CP2 event de-
tection.
This mode is enabled
RLDSEL1=0.
As long as RUNRES bit is set, an external event
on CP2 pin generates both, at firstthe capture into
CP, and then the reload from RLCP. Capture into
CP on CP2 event is enabled only if CP2FLG and
CP2ERR are cleared, otherwise only reload func-
tions from RLCP are performed.
An external event on CP1 activates CP1FLG or
CP1ERR flags without any impact on the reload or
capture functions.
for RLDSEL2=1 and
Note
: After Reset, the first CP2 event will capture
the 0000h state of the counter into CP and then
will restart the counter after loading it from RLCP.
CP2FLG flag must always be cleared to execute
another capture into CP.
Software triggered restart mode with CP2
event detection.
This mode is enabled for RLDSEL2=0 and
RLDSEL1=0.
RUNRES bit setting initiates the reload and start-
up of the downcounting, while CP2 is used as
strobe source for the CT capture into CP register.
Figure 27. . CP2 Triggered Restart Mode with CP2 Event Detection
Figure 28. . Software Triggered Restart Mode with CP2 Event Detection
VR02007C
CP1
No action
Set CP2ERR
First Capture CT into CP
Then Reload CT from RLCP
Set CP2FLG
CP2
Set CP1ERR
Set CP1FLG
Reload CT from RLCP
Reload CT from RLCP
VR02007D
COUNTER
CT
CP1
CP1 disabled
0000h
0000h
Load Counter from RLCP and Startup
RUNRES
Software Reset
Set CP1FLG
CP2 disabled
CP2
Set CP2ERR
CP1 disabled
Set CP1ERR
Capture CT into CP
Set CP2FLG
46
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