參數(shù)資料
型號： ST62E35B
廠商： 意法半導(dǎo)體
英文描述： 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
中文描述： 8位檢察官辦公室/存儲器與阿微控制器/ D轉(zhuǎn)換器，16位自動重加載定時器，EEPROM中，SPI和UART
文件頁數(shù)： 27/82頁
文件大?。?/td> 617K
代理商： ST62E35B
27/82
ST62T35B/E35B
IINTERRUPTS
(Cont’d)
3.3.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused
Bit 6 =
LES
: Level/Edge Selection bit
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
: Edge Selection bit
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 =
GEN
: Global Enable Interrupt When this
bit is set to one, all interrupts are enabled. When
this bit is cleared to zero all the interrupts (exclud-
ing NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.3.4 Interrupt sources
Interrupt
ST62E35B/T35B are summarized in theTable 10
with associated mask bit to enable/disable the in-
terrupt request.
sources
available
on
the
Table 10. Interrupt Requests and Mask Bits
7
0
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
C8h
D4h
D1h
Mask bit
Masked Interrupt Source
Interrupt
source
All
source 4
source 4
GENERAL
TIMER
A/D CONVERTER
IOR
TSCR1
ADCR
GEN
ETI
EAI
RXIEN
TXIEN
OVFIEN
CP1IEN
CP2IEN
ZEROIEN
CMPIEN
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
ORPDn-DRPDn
ORPEn-DRPEn
All Interrupts, excluding NM
I
TMZ: TIMER Overflow
EOC: End of Conversion
RXRDY : Byte received
TXMT : Byte sent
OVFFLG: ARTIMER Overflow
CP1FLG
CP2FLG
ZEROFLG: Compare to zero flag
CMPFLG: Compare flag
End of Transmission
PAn pin
PBn pin
PCn pin
PDn pin
PEn pin
UART
UARTCR
D7h
source 4
ARTIMER
SCR1
SCR2
SCR3
SCR3
SCR3
SPI
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
ORPD-DRPD
ORPE-DRPE
E8h
E1h
E2h
E2h
E2h
DCh
C0h-C4h
C1h-C5h
C2h-C6h
C3h-C7h
FCh-FDh
source 3
SPI
Port PAn
Port PBn
Port PCn
Port PDn
Port PEn
source 1
source 1
source 2
source 0
source 2
source 1
26
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