參數(shù)資料
型號： ST62E35B
廠商： 意法半導體
英文描述： 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
中文描述： 8位檢察官辦公室/存儲器與阿微控制器/ D轉換器，16位自動重加載定時器，EEPROM中，SPI和UART
文件頁數(shù)： 28/82頁
文件大?。?/td> 617K
代理商： ST62E35B
28/82
ST62T35B/E35B
IINTERRUPTS
(Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh
—
Read/Write
In conjunction with IOR register ESB bit, the polar-
ity of I/O pins triggered interrupts can be selected
by setting accordingly the Interrupt Polarity Regis-
ter (IPR). If a bit in IPR is set to one the corre-
sponding port interrupt is inverted (e.g. IPR bit 2 =
1 ; port C generates interrupt on rising edge. At re-
set, IPR is cleared and all port interrupts are not
inverted (e.g. Port C generates interrupts on fall-
ing edges).
Bit 7 - Bits 5 = Unused
Bit 4 = Port E Interrupt Polarity
Bit 3 = Port D Interrupt Polarity
Bit 2 = Port C Interrupt Polarity
Bit 1= Port A Interrupt Polarity
Bit 0 = Port B Interrupt Polarity
Tables 11. I/O Interrupts selections according to IPR, IOR programming
7
0
-
-
-
PortE PortD PortC PortA PortB
GEN
IPR3
IPR0
IOR5
Port B occurence
Port D occurence
Interrupt
source
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
2
GEN
IPR4
IPR1
IOR6
Port A occurence
Port E occurence
Interrupt
source
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
falling edge
low level
rising edge
high level
falling edge
low level
rising edge
high level
Disabled
falling edge
low level
falling edge
low level
rising edge
high level
rising edge
high level
Disabled
1
IPR2
0
1
Port C occurence
falling edge
rising edge
Interrupt source
0
27
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