參數(shù)資料
型號(hào)： ST40RA200XH6E
廠(chǎng)商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372
封裝： 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372
文件頁(yè)數(shù)： 71/94頁(yè)
文件大?。?/td> 2144K
代理商： ST40RA200XH6E
8 Pin description
ST40RA
73/92
MODE7
EADDR9
MD7
EMISS
Enable MPX arbiter
MODE8
EADDR10
MD8
System
Set endianness
H: Little
L: Big
MODE9
EADDR11
MD9
EMI
Set EMI port
H: Master
L: Slave
b
MODE11:
10
EADDR12
EADDR13
MD11:10
EMI
Set booting ROM bus size
00: Reserved
01: 32-bit
10: 16-bit
11: 8-bit
MODE12
EADDR14
MD12
EMI
Enable NOP when accessing flash
c
MODE13
EADDR15
MD13
Reserved
Tie high
d
MODE14
EADDR16
MD14
PCI
PCI bridge mode
H: Host
L: Satellite
MODE15
EADDR17
MD15
PCI
Reserved: PCI select clock
H: External
L: Internal
e
MODE16
EADDR18
MD16
-
Reserved: Tie high
f
MODE17
EADDR19
MD17
-
MODE18
EADDR20
MD18
-
MODE19
EADDR21
MD19
-
a. See CLOCKGEN chapter of the ST40 System Architecture Manual for details.
b. ST40RA is always the clock master, providing EMI clocks to the system.
c. See EMI chapter of the
ST40 System Architecture Manual for details.
d. reserved for enable retiming stage on EMI padlogic
e. PCI clock is selected externally on the board for ST40RA. The mode pin may be used for clock
selection in future variants.
f. These mode pins are not used in current variants, however, they may be used to enable additional
functionality in future variants
Table 37: Mode selection pins for ST40RA
Mode
pin
Pin name
Architecture
signal name
Block
affected
Description
Notes
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