- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98143 > ST40RA200XH6E (STMICROELECTRONICS) 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372 PDF資料下載
參數(shù)資料
| 型號： | ST40RA200XH6E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372 |
| 文件頁數(shù)： | 46/94頁 |
| 文件大?。?/td> | 2144K |
| 代理商： | ST40RA200XH6E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
50/92
ST40RA
6 Clock generation
6.4.1
Programming the PLL output frequency
The three dividers used within the PLL are referred to as M (predivider), N (feedback divider) and P
(postdivider) for brevity. Note that there is a divide-by-2 fixed prescaler before the feedback divider.
The binary values applied to the programmable dividers, and the frequency of CLOCKIN controls
the output frequency of the PLL macrocell:
where the values of M, N and P must satisfy the following constraints:
● Divider limits:
,
● Phase comparator limits:
,
● VCO limit:
,
● M divider limit:
.
For example, if 300 MHz from an input clock of 33 MHz is to be generated, the values of M, N and
P are worked out as below.
1
The phase comparator must operate between 1 MHz and 2 MHz, so choose M = 22 (for
1.5 MHz operation).
2
The VCO needs to run between 200 MHz and 622 MHz. It could be run at 300 MHz directly
(which takes a little less current), or at 600 MHz then divide by 2 to ensure an exact 50% duty
cycle. In this example 600 MHz is chosen so N = 200.
3
The postdivider then needs to be a divide by 2. This is programmed in powers of 2, so P = 1.
The P divider changes value without glitching of the output clock.
6.4.2
Changing clock frequency
The clock frequencies are changed in two ways.
● Change the core PLL frequencies.
The PLL must be stopped, the control register reconfigured with the new settings, and the PLL
restarted at the new frequency.
● Change the frequency division ratio of the clock domains.
The control registers are changed dynamically and the new frequencies are effective
immediately.
6.4.3
Changing the core PLL frequencies
This procedure applies to either CLOCKGENA or CLOCKGENB and to PLL1 or PLL2.
1
Stop the PLL. The CLOCKGENA.PLL1CR2.STBPLLENSEL register selects whether the PLL
is enabled by the CLOCKGENA.PLL1CR2.STBPLLEN or the CPG.FRQCR.PLL1EN register.
2
Reconfigure the PLL. Set the CLOCKGENA.PLL1CR1 register to one of the supported
configurations on the datasheet.
3
Restart the PLL, following the procedure described in the ST40 System Architecture Volume 1:
System.
F clockout
()
2N
×
M2P
×
------------------
F clockin
()
×
=
1
M
255 1
N
255 0
P
5
≤≤
,
≤≤
,
≤≤
1MHz
F clockin
()
M
-----------------------------
2MHz
≤≤
200MHz
2N
×
M
-------------
F clockin
()
×
622MHz
≤≤
F clockin
() 200MHz
≤
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52510F3M6 | MICROCONTROLLER, PDSO20 |
| ST52E430B/D | 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32 |
| ST52F510F1M6 | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO20 |
| ST52F510G0B6 | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDIP28 |
| ST52F513F0M6 | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST40RP | 功能描述:兩端交流開關(guān)元件 ST40RP RoHS:否 制造商:STMicroelectronics 轉(zhuǎn)折電流 VBO:45 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23 封裝:Reel |
| ST40-TOOLSET/WIN | 制造商:STMicroelectronics 功能描述:ST40-TOOLSET/WIN - Bulk |
| ST40X-10S-CV | 制造商:Hirose 功能描述: |
| ST40X-10S-CV(80) | 功能描述:I/O 連接器 10P CBLE PLUG STD SOLDER SHIELDED RoHS:否 制造商:Hirose Connector 產(chǎn)品:Plugs 系列:DH 端口數(shù)量: 位置/觸點數(shù)量:51 節(jié)距:1 mm 觸點電鍍: 觸點材料: 型式:Male 電流額定值:0.5 A 安裝風(fēng)格:Cable 端接類型:IDC 顏色: 安裝角: |
| ST40X-10S-CVR | 制造商:HRS 制造商全稱:HRS 功能描述:Interface Connectors for Miniature, Portable Terminal Devices |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。