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參數(shù)資料
| 型號(hào)： | ST40RA200XH6E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372 |
| 文件頁(yè)數(shù)： | 24/94頁(yè) |
| 文件大?。?/td> | 2144K |
| 代理商： | ST40RA200XH6E |
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ST40RA
5 System configuration
5.3.3
ST40RA I/O device interrupt allocation
5.4
GPDMA channel mapping
For full details of the GPDMA controller see ST40 System Architecture Manual Volume 1: System.
The ST40RA general purpose DMA controller channel map is shown in Table 9.
Table 8: Mailbox and EMPI interrupt allocation
Interrupt source
INTEVT
code
Interrupt priority
IPR
bit numbers
Priority
within IPR
setting unit
Value
Initial value
Mailbox
MAILBOX
0x1000
0 to 15
0
INTPRI04[0:3]
High to low
Reserved
0 to 15
0
INTPRI04[27:24]
High to low
EMPI
INV_ADDR
0x1380
0 to 15
0
INTPRI04[31:28]
High to low
Reserved
Table 9: GPDMA request number allocation
Request
number
Associated
device
Protocol
Comment
0
External device 0
DREQ or
DREQ/DRACK
The following pins are available for external peripherals:
DREQ[0:1],
DACK[0:1],
DRAK[0:1].
1
External device 1
DREQ or
DREQ/DRACK
2 and 3
Reserved
4
SCIF1 transmit
DREQ
This allow SCIF to memory and memory to SCIF transfer
to be supported on any DMA channel.
5
SCIF1 received
DREQ
6
SCIF2 transmit
DREQ
7
SCIF2 receive
DREQ
8
TMU
DREQ/DRACK
Typically used to trigger or pace memory transfers.
9 and 10
Reserved
11
PCI1
DREQ or
DREQ/DRACK
May be used to improve the efficiency of transfers to and
from the PCI.
12
PCI2
DREQ or
DREQ/DRACK
13
PCI3
DREQ or
DREQ/DRACK
14
PCI4
DREQ or
DREQ/DRACK
15 to 31
Reserved
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