- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98143 > ST40RA150XH6 (STMICROELECTRONICS) 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372 PDF資料下載
參數(shù)資料
| 型號(hào)： | ST40RA150XH6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372 |
| 封裝： | 27 X 27 MM, BGA-372 |
| 文件頁(yè)數(shù)： | 9/90頁(yè) |
| 文件大?。?/td> | 672K |
| 代理商： | ST40RA150XH6 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)
4 System configuration
ST40RA166
17/88
4.3.3
ST40RA166 I/O device interrupt allocation
4.4
GPDMA channel mapping
For full details of the GPDMA controller see
ST40 Architecture Manual Volume 1: System.
The ST40RA166 general purpose DMA controller channel map is shown in
Table 5.
Interrupt source
INTEVT
code
Interrupt priority
IPR
bit numbers
Priority
within IPR
setting unit
Value
Initial value
Mailbox
MAILBOX
0x1000
0 to 15
0
INTPRI
04[0:3]
High to low
Reserved
0 to 15
0
INTPRI
04[27:24]
High to low
EMPI
INV
_ADDR
0x1380
0 to 15
0
INTPRI
04[31:28]
High to low
Reserved
Table 4: Mailbox and EMPI interrupt allocation
Request
number
Associated
device
Protocol
Comment
0
External device 0
DREQ or
DREQ/DRACK
The following pins are available for external peripherals:
DREQ
[0:1],
DACK
[0:1],
DRAK
[0:1].
1
External device 1
DREQ or
DREQ/DRACK
2 and 3
Reserved
4
SCIF1 transmit
DREQ
This allow SCIF to memory and memory to SCIF transfer
to be supported on any DMA channel.
5
SCIF1 received
DREQ
6
SCIF2 transmit
DREQ
7
SCIF2 receive
DREQ
8
TMU
DREQ/DRACK
Typically used to trigger or pace memory transfers.
9 and 10
Reserved
11
PCI1
DREQ or
DREQ/DRACK
May be used to improve the efficiency of transfers to and
from the PCI.
12
PCI2
DREQ or
DREQ/DRACK
13
PCI3
DREQ or
DREQ/DRACK
14
PCI4
DREQ or
DREQ/DRACK
15 to 31
Reserved
Table 5: GPDMA request number allocation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST40RA200XH6E | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA372 |
| ST52510F3M6 | MICROCONTROLLER, PDSO20 |
| ST52E430B/D | 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32 |
| ST52F510F1M6 | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO20 |
| ST52F510G0B6 | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST40RA150XHA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-bit Embedded SuperH Device |
| ST40RA166 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-BIT EMBEDDED SUPERH MICROPROCESSOR |
| ST40RA166XH1 | 制造商:STMicroelectronics 功能描述: |
| ST40RA166XH6 | 制造商:STMicroelectronics 功能描述:32-BIT SUPERH CPU - Trays |
| ST40RA166XH6/TR | 制造商:STMicroelectronics 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。