參數(shù)資料
型號: ST40RA150XH6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372
封裝: 27 X 27 MM, BGA-372
文件頁數(shù): 72/90頁
文件大?。?/td> 672K
代理商: ST40RA150XH6
74/88
ST40RA166
A Interconnect architecture
A.1
Arbitration schemes
A.1.1
PCI arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) for fixed priority mode has to be in the following priority order:
q
CPU buffer,
q
EMPI,
q
GPDMA,
q
PCI (PCI master request, although not expected, get served to avoid deadlock).
The priority orders have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.2
EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI)
The default configuration (after reset) for fixed priority mode has to be in the following priority order:
q
CPU buffer,
q
PCI,
q
EMPI,
q
GPDMA.
The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.3
LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:
q
CPU,
q
GPDMA and PCI buffer.
The priority orders have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.4
PER arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:
q
CPU buffer,
q
PCI,
q
EMPI,
q
GPDMA.
The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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