參數(shù)資料
型號: ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁數(shù): 93/116頁
文件大?。?/td> 1107K
代理商: ST20GP6
ST20-GP1
93/116
16 Configuration register addresses
This chapter lists all the ST20-GP1 configuration registers and gives the addresses of the registers.
The complete bit format of each of the registers and its functionality is given in the relevant chapter.
The registers can be examined and set by the devlw (device load word) and devsw (device store
word) instructions. Note, they cannot be accessed using memory instructions.
Register
Address
Size
Set
Clear
Read/
Write
HandlerWptr0
#20000000
32
R/W
HandlerWptr1
#20000004
32
R/W
HandlerWptr2
#20000008
32
R/W
HandlerWptr3
#2000000C
32
R/W
HandlerWptr4
#20000010
32
R/W
TriggerMode0
#20000040
3
R/W
TriggerMode1
#20000044
3
R/W
TriggerMode2
#20000048
3
R/W
TriggerMode3
#2000004C
3
R/W
TriggerMode4
#20000050
3
R/W
Pending
#20000080
5
Interrupt trigger
Interrupt grant
R/W
Set_Pending
#20000084
5
W
Clear_Pending
#20000088
5
W
Mask
#200000C0
17
R/W
Set_Mask
#200000C4
17
W
Clear_Mask
#200000C8
17
W
Exec
#20000100
5
Interrupt valid
Interrupt done
R/W
Set_Exec
#20000104
5
W
Clear_Exec
#20000108
5
W
LPTimerLS
#20000400
32
R/W
LPTimerMS
#20000404
32
R/W
LPTimerStart
#20000408
1
By a write to
LP-
TimerLS
or
LP-
TimerMS
R/W
LPAlarmLS
#20000410
32
R/W
LPAlarmMS
#20000414
8
R/W
LPAlarmStart
#20000418
1
R/W
LPSysPll
#20000420
2
R/W
SysRatio
#20000500
#20000510
6
1
R
R/W
WdEnable
Table 16.1 ST20-GP1 configuration register addresses
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