參數(shù)資料
型號(hào): ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁數(shù): 106/116頁
文件大小: 1107K
代理商: ST20GP6
ST20-GP1
106/116
19.4 ClockIn timings
Notes
1
2
3
Measured between corresponding points on consecutive falling edges.
Variation of individual falling edges from their nominal times.
Clock transitions must be monotonic within the range V
IH
to V
IL
(see Electrical Specifica-
tions).
Table 19.4
ClockIn
timings
Figure 19.5
ClockIn
timings
19.4.1 ClockIn frequency
Nominal
ClockIn
frequency is 16.36800 Mhz
±
50 ppm tolerance. This tolerance relates to the GPS
system requirements and not for the device to function.
Symbol
Parameter
Min
Nom
Max
Units
Notes
t
DCLDCH
ClockIn
pulse width low for PLL operation
18
42.5
ns
t
DCHDCL
ClockIn
pulse width high for PLL operation
18
42.5
ns
t
DCr
ClockIn
rise time for PLL operation
20
ns
3
t
DCf
ClockIn
fall time for PLL operation
20
ns
3
t
GDVCH
GPSIF
valid before clock rising edge
20
ns
t
CHGDX
GPSIF
valid after clock rising edge
0
ns
90%
10%
t
DCr
2.0V
1.5V
0.8V
t
DCLDCH
t
DCHDCL
t
DCf
90%
10%
t
GDVCH
t
CHGDX
GPSIF
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