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1.7.6
On-chip peripherals
On-chip peripherals may have memory-mapped registers in the address range
PeripheralStart to PeripheralEnd. Access to these registers is represented in the
following way:
PeripheralByte[
address] references an 8-bit peripheral register
PeripheralSixteen[
address] references a 16-bit peripheral register
PeripheralWord[
address] references a 32-bit peripheral register
For all of these, the state of the peripheral referenced is that
before the instruction if
the function is used without a prime (e.g. PeripheralWord[]), and that
after the
instruction if the function is used with a prime (e.g. PeripheralWord
′[]).
For example, writing a value given by an expression,
expr, to the register at address
addr is represented by:
PeripheralWord
′[addr] ← expr
and reading a word from a peripheral is achieved by:
Areg
′← PeripheralWord[addr]
1.8
Block move registers
A group of registers is used in the implementation of block moves. These are referred
to as the ‘block move registers’ and include
Move2dBlockLength, Move2dDestStride,
and
Move2dSourceStride.
1.9
Constants
A number of data structures have been defined in this book. Each compr ises a
number of data slots that are referenced by name in the text and the following
instructions descriptions.
These data structures is listed in Table 1.2 to Table 1.4.
word offset
slot name
purpose
0
pw.Temp
slot used by some instructions for storing temporary values
-1
pw.Iptr
the instruction pointer of a descheduled process
-2
pw.Link
the address of the workspace of the next process in scheduling list
-3
pw.Pointer
saved pointer to communication data area
-3
pw.State
saved alternative state
-4
pw.TLink
address of the workspace of the next process on the timer list
-5
pw.Time
time that a process on a timer list is waiting for
Table 1.1 Process workspace data structure