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參數(shù)資料
| 型號： | SSTUG32868ET/G |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176 |
| 封裝： | 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 166K |
| 代理商： | SSTUG32868ET/G |
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SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
17 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
10. Characteristics
[1]
Instantaneous is dened as within < 2 ns following the output data transition edge.
Table 8.
Characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH = 6 mA; VDD = 1.7 V
1.2
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
0.5
V
II
input current
all inputs; VI =VDD or GND; VDD = 1.9 V
-
±5
A
IDD
supply current
static standby; RESET = GND; VDD = 1.9 V;
IO =0mA
--
2
mA
static operating; RESET = VDD;
VDD = 1.9 V; IO = 0 mA;
VI =VIH(AC) or VIL(AC)
-
80
mA
IDDD
dynamic operating current
per MHz
clock only; RESET = VDD;
VI =VIH(AC) or VIL(AC); CK and CK switching
at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V
-16
-
A
per each data input (1 : 1 mode);
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
VDD = 1.8 V
-19
-
A
per each data input (1 : 2 mode);
RESET = VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
VDD = 1.8 V
-19
-
A
Ci
input capacitance
Dn, CSGEN, PAR_IN inputs;
VI =Vref ± 250 mV; VDD = 1.8 V
2.5
-
4
pF
DCSn; VICR = 0.9 V; VID = 600 mV;
VDD = 1.8 V
2.5
-
4
pF
CK and CK; VICR = 0.9 V; VID = 600 mV;
VDD = 1.8 V
2-
3
pF
RESET; VI =VDD or GND; VDD = 1.8 V
3
-
5
pF
Zo
output impedance
instantaneous
[1] -7
-
steady-state
-
53
-
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| SSTUG32868ETS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications |
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| SSTUH32864EC,518 | 功能描述:寄存器 1.8V CONFIG REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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