參數(shù)資料
型號: SSTUG32868ET/G
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
封裝: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁數(shù): 11/29頁
文件大?。?/td> 166K
代理商: SSTUG32868ET/G
SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
19 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
Pulse Repetition Rate (PRR)
≤ 10 MHz; Z
0 =50 ; input slew rate = 1 V/ns ± 20 %,
unless otherwise specied.
The outputs are measured one at a time with one transition per measurement.
(1) CL includes probe and jig capacitance.
Fig 9.
Load circuit, data output measurements
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 10. Voltage and current waveforms; inputs active and inactive times
VID = 600 mV.
VIH =Vref + 250 mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
VIL =Vref 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; pulse duration
RL = 100
RL = 1000
VDD
50
CK inputs
CK
OUT
DUT
test point
002aab902
test point
delay = 350 ps
Zo = 50
RL = 1000
CL = 30 pF(1)
LVCMOS
RESET
10 %
IDD(1)
tINACT
VDD
0.5VDD
tACT
90 %
0 V
002aaa372
0.5VDD
VICR
VIH
VIL
input
tW
VID
002aaa373
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