參數(shù)資料
型號(hào)： SSTUG32868ET/G
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
封裝： 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁(yè)數(shù)： 3/29頁(yè)
文件大?。?/td> 166K
代理商： SSTUG32868ET/G
SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
11 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
[1]
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
[2]
PAR_IN arrives one clock cycle after the data to which it applies.
[3]
This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
[4]
QERR0 is the previous state of output QERR.
[5]
If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on
the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus
two clock cycles or until RESET is driven LOW.
7.2 Functional information
The SSTUG32868 is a 28-bit 1 : 2 congurable registered buffer designed for 1.7 V to
1.9 V VDD operation.
All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All
outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specications, except the open-drain error (QERR) output.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (oating) data, clock, and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and
all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always
must be held at a valid logic HIGH or LOW level.
To ensure dened outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specied to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be ensured between the two.
When entering reset, the register will be cleared and the data outputs will be driven LOW
quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
Table 5.
Parity and standby function table
Inputs
Output
RESET
DCS0[1]
DCS1[1]
CK
∑ of inputs = H
(D1 to D28)
QERR[3][4]
HL
X
↑↓
even
L
H
HL
X
↑↓
odd
L
HL
X
↑↓
even
H
L
HL
X
↑↓
odd
H
HX
L
↑↓
even
L
H
HX
L
↑↓
odd
L
HX
L
↑↓
even
H
L
HX
L
↑↓
odd
H
HH
H
↑↓
XX
QERR0[5]
H
X
L or H
X
QERR0
L
X or oating
X
X or oating
H
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTUG32868ETS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
SSTUG32868G 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
SSTUH32864 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications
SSTUH32864EC 功能描述:寄存器 1.8V CONFIG REG BUFFER/DDRII RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTUH32864EC,518 功能描述:寄存器 1.8V CONFIG REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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