參數(shù)資料
型號: SSTE32882HLBAKG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù): 59/69頁
文件大?。?/td> 1263K
代理商: SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
62
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Calculating the virtual VTT crossing point
tDIS
tEN = t1a + y1a(t1a-t2a)/(y2a-y1a)
VOL
VOH
VTT
y1b
y2b
actual waveform
y1b
y2b
t2b
t1b
UCK=UCK
y2a
y1a
tEN
t2a
t1a
Yn
tDIS = t1b + y1b(t1b-t2b)/(y2b-y1b)
VTT=VDD/2
相關(guān)PDF資料
PDF描述
SSTE32882HLBBKG SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
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SSTUA32866EC/G 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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