參數(shù)資料
型號(hào)： SSTE32882HLBAKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 11/69頁
文件大小： 1263K
代理商： SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
19
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
IOL
LOW-level output current
Qn5
11
mA
Yn, Yn, FBOUT, FBOUT
11
mA
ERROUT
25
mA
IDD6
Static standby current
RESET = GND and CK = CK = VIL(AC)5
mA
Low-Power Static Operating
RESET =VDD and CK = CK = VIL(AC), MIRROR =
VDD, DCS[1:0] = [0,1]
15
mA
ICCD
Dynamic operating -- input clock
only; active outputs
RESET =VDD, MIRROR = VDD, VI = VIH(AC) or
VIL(AC), RC0[DBA0]=0, RC0[DBA1]=0, CK and CK
switching 50% duty cycle, IO = 0, DCS0 = L, DCS1
= H. VDD = VDDMAX
68
μA/MHz
Dynamic operating -- per each
data input
RESET =VDD, MIRROR = VDD, VI = VIH(AC) or
VIL(AC), CK and CK switching 50% duty cycle. One
data input switching at one half clock frequency,
50% duty cycle; RC0[DBA0]=0, RC0[DBA1]=0, IO =
0, DCS0 = L, DCS1 = H. VDD = VDDMAX
16
μA/Clock
MHz/
D Input
1
The RESET and MIRROR inputs of the device must be held at valid voltage levels (not floating) to ensure prop-
er device operation. The differential inputs must not be floating unless RESET is LOW.
2
All typical values are at VDD = 1.5V, TA = 25°C.
3
DCKEn, DODTn, DAn, DBAn, DRAS, DCAS, DWE, DCSn, PAR_IN are measured while RESET is pulled LOW.
4
The CK and CK inputs have pull-down resistors in the range of 10K
Ω to 100KΩ.
5
Qn = QxAn, QxCSn, QxCKEn, QxODTn, QxRAS, QxCAS, QxWE, and QxBAn.
6
The supply current is measured as the total current consumptoion on the AVDD, PVDD, and VDD supply current
pins. Io = 0.
Symbol
Parameter1
Conditions
Min
Typ2
Max
Unit
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SSTE32882HLBBKG SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBAKG8 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882HLBAKG8/M 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel
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SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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