參數(shù)資料
型號(hào)： SSTE32882HLBAKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 50/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
54
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
The IBT control is also located in this control word, with two options of 100
Ω or 150Ω which can be selected to
adapt to different system scenarios. At power-up, the SSTE32882KA1 IBT defaults to 100
Ω. The system controller
can reprogram the termination resistance to 150
Ω by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE,
DCSn, DODTn, DCKEn, and PAR_IN inputs have the IBT. The CK, CK, FBIN, FBIN, RESET, and MIRROR inputs
do not have IBT.
If MIRROR is ‘HIGH’ then it is assumed the register is located on the back side of a module where two registers are
tied together on the input side. In this case, for the register on the back side, the IBT are turned off on all inputs
except the DCSn and DODTn inputs.
The following diagram illustrates the pre-launch feature whereby double loaded nets in a 2-rank configuration can
be driven with an earlier signal compared to output clock and control in order to compensate for the slower signal
travel speed. This timing applies at all supported frequencies.
Effective IBT Tolerance Requirement
Min
Max
Total Effective IBT Value Tolerance1
1 Example: for 100 Ohm IBT, Min = 90 Ohms, Max = 110 Ohms
-10%
+10%
Mismatch Tolerance Between R-IBT-Up and R-IBT-Down
Max
Mismatch Tolerance Between R-IBT-Up
and R-IBT-Down1
1 (1 - R-IBT-Up/R-IBT-Down) *100% < ABS(5%)
ABS(5%)
相關(guān)PDF資料
PDF描述
SSTE32882HLBBKG SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
SSTUA32864EC,557 SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUA32866EC/G 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBAKG8 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882HLBAKG8/M 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel
SSTE32882HLBBKG 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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