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參數(shù)資料
| 型號： | SSTE32882HLBAKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 26/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBAKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
32
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
From a device perspective, the initialization sequence must be as shown in the following Device Initialization table.
SSTE32882KA1 Device Initialization Sequence1.
1. x=Logic low or lolgic high. Z=floating.
2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
3. The feedback clock (FBOUT and FBOUT) pins may or may not be actively driven by the device.
4. The system may power up using either 1.5V or 1.35V. The BIOS reads the SPD and adjusts the voltage if needed from 1.35V to 1.5V or from 1.5V to 1.35V. After the voltage
transition, stable power is provided for a minimum of 200 uS with RESET asserted.
5. QxCKEn and ERROUT will be driven to these logic states by the register after RESET is driven low and VDD is 1.5V or 1.35V (nominal).
6. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge, within (tSTAB - tACT)
us, the state of QxODTx is a function of DODTx (high or low).
7. Step 7 is a typical usage example and is not a register requirement.
Reset Initialization with Stable Power
The timing diagram in the following diagram depicts the initialization sequence with stable power and clock. This will
apply to the situation when we have a soft reset in the system. RESET will be asserted for minimum 100ns. This
RESET timing is based on DDR3 DRAM Reset Initialization with Stable Power requirement, and is a minimum
requirement. Actual RESET timing can vary base on specific system requirement, but it cannot be less than 100ns
as required by JESD79-3 Specification.
Step
Power
Inputs: Signals provided by the controller
Outputs: Signals provided by the device
VDD, AVDD,
PVDD
RESET
Vref
DCS
[n:0]2
DODT
[0:1]
DCKE
[0:1]
DA/C
PAR_IN CK,CK
QCS
[n:0]2
QODT
[0:1]
QCKE
[0:1]
QxA/C ERROUT
Y[0:3]
FB
OUT3
0
0V
X or Z
X or Z X or Z X or Z X or Z X or Z
X or Z
Z
1
0-->VDD
X or Z
X or Z X or Z X or Z X or Z X or Z
L
X or
Z
X or Z
X or
Z
X or Z
24
VDD
1.5V-->1.35V
1.35V-->1.5V
L
X or Z
X or Z X or Z X or Z X or Z X or Z
L
Z
L5
Z
H5
ZZ
3
VDD
L
X or Z
X or Z X or Z X or Z X or Z X or Z running
ZZ
LZ
HZ
Z
4
VDD
L
X or Z
H
X or Z
L
X or Z X or Z running
Z
LZ
HZ
Z
5
VDD
L
stable
voltage
HX
L
XX
running
Z
LZ
HZ
Z
6
VDD
H
stable
voltage
HX
L
XX
running
H
L6
LX
H
running running
77
VDD
H
stable
voltage
H
X
running
After Step 6 (Step 7 and beyond), the device outputs are as defined in
the device Function Tables.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBAKG8 | 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882HLBAKG8/M | 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel |
| SSTE32882HLBBKG | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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