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參數(shù)資料
| 型號(hào)： | SSTE32882HLBAKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 44/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBAKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
49
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Control Words
The device features a set of control words, which allow the optimization of the device properties for different raw
card designs. The different control words and settings are described below. Any change to these control words
requires some time for the device to settle. For changes to the control word setting, except for RC2 (bits DBA1 and
DA3) and RC10, the controller needs to wait tMRD after the last control word access, before further access to the
DRAM can take place. For any changes to the clock timing (RC2: bits DBA1 and DA3) and RC10, this settling may
take up to tSTAB time. All chip select inputs (DCS[n:0]) must be kept high during that time. The Control Words can
be accessed and written to when running within any one defined frequency band.
CONTROL WORD DECODING
The values to be programmed into each control word are presented on signals DA3, DA4, DBA0 and DBA1
simultaneously with the assertion of the control word access through DCS0 and DCS1, or DCS2 and DCS3 in the
QuadCS enabled mode, and the address of the control word on DA0, DA1, DA2 and DBA2.
The reset default state of Control Words 0 .. 5 and Control Words 8 .. 15 is “0”. The reset default state for Control
Words 6 and 7 is vendor specific. Every time the device is reset, its default state is restored. Stopping the clocks
(CK = CK = low) to put the device in low-power mode will not alter the control word settings.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBAKG8 | 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882HLBAKG8/M | 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel |
| SSTE32882HLBBKG | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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