參數(shù)資料
型號(hào): SST89V58RD2-33-I-TQJE
廠商: Microchip Technology
文件頁(yè)數(shù): 76/92頁(yè)
文件大小: 0K
描述: IC MCU 8BIT 40KB FLASH 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤(pán)
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
78
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Figure 34:IDD vs. Frequency for 3V SST89V5xRD2/RD
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and
3. The noise due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transi-
tions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may
exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a
Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF.
4. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7
specification when the address bits are stabilizing.
5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition cur-
rent reaches its maximum value when VIN is approximately 2V.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
30
25
20
15
10
5
0
510
15
20
2530
35
I DD
(mA)
Internal Clock Frequency (MHz)
Maximum Idle IDD
Typical Idle IDD
Maximum Active IDD
Typical Active IDD
1255
F33.0
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