參數(shù)資料
型號(hào)： SST89V58RD2-33-I-TQJE
廠商： Microchip Technology
文件頁數(shù)： 22/92頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 40KB FLASH 44TQFP
標(biāo)準(zhǔn)包裝： 160
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
29
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Symbol
Function
SPIE
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.
DORD
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
MSTR
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
CPOL
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
CPHA
Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data
relationship between master and slave. See Figures 21 and 22.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPR1, SPR0
SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured
as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK
and the oscillator frequency, fOSC, is as follows:
Symbol
Function
SPIF
SPI Interrupt Flag.
Upon completion of data transfer, this bit is set to 1.
If SPIE =1 and ES =1, an interrupt is then generated.
This bit is cleared by software.
WCOL
Write Collision Flag.
Set if the SPI data register is written to during data transfer.
This bit is cleared by software.
SPI Control Register (SPCR)
Location
76
54
32
10
Reset
Value
D5H
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
00H
SPR1
SPR0
SCK = fOSC divided by
0
1
0
1
0
1
4
16
64
128
SPI Status Register (SPSR)
Location
76543210
Reset
Value
AAH
SPIF
WCOL
------
00xxxxxxb
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