參數(shù)資料
型號(hào)： SST89V58RD2-33-I-TQJE
廠商： Microchip Technology
文件頁(yè)數(shù)： 29/92頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 40KB FLASH 44TQFP
標(biāo)準(zhǔn)包裝： 160
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 8K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤(pán)
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
35
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Block 1, then the target address is implicitly defined to be in Block 0. If the IAP operation originates
from external program space, then, the target will depend on the address and the state of bank selec-
tion.
IAP Enable Bit
The IAP enable bit, SFCF[6], enables in-application programming mode. Until this bit is set, all flash
programming IAP commands will be ignored.
In-Application Programming Mode Commands
All of the following commands can only be initiated in the IAP mode. In all situations, writing the control
byte to the SFCM register will initiate all of the operations. All commands will not be enabled if the
security locks are enabled on the selected memory block.
The Program command is for programming new data into the memory array. The portion of the mem-
ory array to be programmed should be in the erased state, FFH. If the memory is not erased, it should
first be erased with an appropriate Erase command.
Warning: Do not attempt to write (program or erase) to a block that the code is currently fetch-
ing from. This will cause unpredictable program behavior and may corrupt program data.
Chip-Erase
The Chip-Erase command erases all bytes in both memory blocks. This command is only allowed
when EA#=0 (external memory execution). Additionally this command is not permitted when the
device is in level 4 locking. In all other instances, this command ignores the Security Lock status and
will erase the security lock bits and re-map bits.
Figure 9: Chip-Erase
Set-Up
MOV SFDT, #55H
Interrupt scheme
MOV SFCM, #81H
Polling scheme
MOV SFCM, #01H
INT1 interrupt
indicates completion
SFST[2] indicates
operation completion
IAP Enable
ORL SFCF, #40H
1255 F08.0
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