參數(shù)資料
型號(hào): SST85LD0512-60-RI-LBTE
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝: 12 X 24 MM, ROHS COMPLIANT, MO-210, LBGA-91
文件頁(yè)數(shù): 11/36頁(yè)
文件大?。?/td> 913K
代理商: SST85LD0512-60-RI-LBTE
2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
19
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Word 65: Minimum Multi-word DMA Transfer Cycle Time Per Word
This field defines the minimum Multi-word DMA transfer cycle time per word. This field defines, in
nanoseconds, the minimum cycle time that the NANDrive supports when performing Multi-word DMA
transfers on a per word basis. SST’s NANDrive supports up to Multi-word DMA Mode-2, so this field is
set to 120ns.
Word 66: Device Recommended Multi-word DMA Cycle Time
This field defines the NANDrive recommended Multi-word DMA transfer cycle time. This field defines,
in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing
a multiple sector READ DMA or WRITE DMA command for any location on the media under nominal
conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the
NANDrive may negate DMARQ for flow control. The rate at which DMARQ is negated could result in
reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control
will not be used, but implies that higher performance may result. SST’s NANDrive supports up to Multi-
word DMA Mode-2, so this field is set to 120 ns.
Word 67: Minimum PIO Transfer Cycle Time Without Flow Control
This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the device guaran-
tees data integrity during the transfer without utilization of IORDY flow control. If this field is supported,
Bit 1 of word 53 shall be set to one.The NANDrive’s minimum cycle time is 120 ns. A value of 0078H is
reported.
Word 68: Minimum PIO Transfer Cycle Time With IORDY
This field defines, in nanoseconds, the minimum cycle time that the device supports while performing data
transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one. The
NANDrive’s minimum cycle time is 120 ns, e.g., PIO Mode-4. A value of 0078H is reported.
Word 80: Major Version Number
If not 0000H or FFFFH, the device claims compliance with the major version(s) as indicated by bits
[6:1] being set to one. Since ATA standards maintain downward compatibility, a device may set more
than one bit. SST55VD020 supports ATA-1 to ATA-6.
Word 81: Minor Version Number
If an implementer claims that the revision of the standard they used to guide their implementation does
not need to be reported or if the implementation was based upon a standard prior to the ATA-3 stan-
dard, word 81 should be 0000H or FFFFH.
A value of 0019H reported in word 81 indicates ATA-6 T13 1410D revision 3a guided the implementa-
tion.
相關(guān)PDF資料
PDF描述
SST85LD1001T-60-RI-LBTE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
SST85LD1004T-60-RI-LBTE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
SST85LD1008M-60-PC-LBTE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
SST85LD1008M-60-PC-LBTE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
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