參數(shù)資料
型號: SST55LD040M-133-C-BZJE
元件分類: 存儲控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA145
封裝: 12 X 12 MM, 1.07 MM HEIGHT, ROHS COMPLIANT, TFBGA-145
文件頁數(shù): 36/39頁
文件大小: 589K
代理商: SST55LD040M-133-C-BZJE
6
Advance Information
NAND Controller
SST55LD040M
2010 Silicon Storage Technology, Inc.
S71408-01-000
04/10
TABLE
1: Pin Assignments (1 of 4)
Symbol
Ball No.
Ball
Type
I/O
Type
Name and Functions
145
TFBGA
Host Interface
A2
F2
I
I1Z
A[2:0] are used to select one of eight registers in the Task File.
A1
G14
A0
F12
D15
H2
I/O
I1Z/O2
D[15:0] Data bus
D14
H1
D13
J3
D12
J2
D11
J1
D10
K2
D9
K1
D8
L2
D7
L13
D6
K14
D5
K13
D4
K12
D3
J14
D2
J13
D1
J12
D0
H14
RESET#
L14
I
I2U
This input pin is the active low hardware reset from the host.
DASP#
L1
I/O
I1U/O4
The Drive Active/Slave Present signal in the Master/Slave handshake protocol.
IORDY
H3
O
O2
IORDY: When in PIO mode, the device is not ready to respond to a data
transfer request. This signal is negated to extend the Host transfer cycle
from the assertion of IORD# or IOWR#. However, it is never negated by
this controller. (This pin supports three functions)
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal is
asserted by the device to indicate that the device is ready to receive Ultra
DMA data-out bursts. The device may negate DDMARDY# to pause an
Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Write is active, this signal is the
data-in strobe generated by the device. Both the rising and falling edges of
DSTROBE cause data to be latched by the host. The device may stop gen-
erating DSTROBE edges to pause an Ultra DMA data-in burst.
CS1FX#
F13
II2Z
CS1FX# is the chip select for the task file registers.
CS3FX#
F1
CS3FX# is used to select the Alternate Status register and the Device
Control register.
CSEL
G2
I
I1U
This internally pulled-up signal is used to configure this device as a Master
or a Slave. When this pin is grounded, this device is configured as a Mas-
ter. When the pin is open, or tied to VDDQ, this device is configured as a
Slave. The pin setting should remain the same from Power-on to Power-
down.
DMARQ
H13
O
O2
DMA Request to host
INTRQ
G13
O
O2
Ready/Busy or Interrupt Request to the host.
DMACK#
G12
I
I2U
DMA Acknowledge - input from host
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