參數(shù)資料
型號(hào): SST55LD040M-133-C-BZJE
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA145
封裝: 12 X 12 MM, 1.07 MM HEIGHT, ROHS COMPLIANT, TFBGA-145
文件頁數(shù): 11/39頁
文件大?。?/td> 589K
代理商: SST55LD040M-133-C-BZJE
Advance Information
NAND Controller
SST55LD040M
2010 Silicon Storage Technology, Inc.
S71408-01-000
04/10
19
Word 63: Multi-word DMA Transfer Mode
This field identifies the multi-word DMA transfer modes supported by the NAND Controller and indicates the
mode that is currently selected. Only one DMA mode can be selected at any given time.
Bit
Function
15-11
Reserved
10
Multi-word DMA mode 2 selected
1: Multi-word DMA mode 2 is selected and bits 8 and 9 are cleared to 0
0: Multi-word DMA mode 2 is not selected.
9
Multi-word DMA mode 1 selected
1: Multi-word DMA mode 1 is selected and 8 and 10 should be cleared to 0.
0: Multi-word DMA mode 1 is not selected.
8
Multi-word DMA mode 0 selected
1: Multi-word DMA mode 0 is selected and bits 9 and 10 are cleared to 0.
0: Multi-word DMA mode 0 is not selected.
7-3
Reserved
2
Multi-word DMA mode 2 supported
1: Multi-word DMA mode 2 and below are supported and Bits 0 and 1 are set to 1.
1
Multi-word DMA mode 1 supported
1: Multi-word DMA mode 1 and below are supported.
0
Multi-word DMA mode 0 supported
1: Multi-word DMA mode 0 is supported.
Word 64: Advanced PIO Data Transfer Mode
Bits [7:0] is defined as the PIO data and register transfer supported field. If this field is supported, bit 1 of word
53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this field by the device
to indicate the PIO modes the device is capable of supporting. Of these bits, bits [7:2] are Reserved for future
PIO modes.
Bit
Function
0
1: NAND Controller supports PIO Mode-3.
1
1: NAND Controller supports PIO Mode-4.
Word 65: Minimum Multi-word DMA Transfer Cycle Time Per Word
This field defines the minimum Multi-word DMA transfer cycle time per word. This field defines, in nanoseconds,
the minimum cycle time that the NAND Controller supports when performing Multi-word DMA transfers on a per
word basis. NAND Controller supports Multi-word DMA Mode-2, so this field is set to 120ns.
Note: NAND Controller is capable of supporting Multi-word DMA Mode-2 cycle time of 80ns
(0050H). Contact SST sales for more details.
Word 66: Device Recommended Multi-word DMA Cycle Time
This field defines the NAND Controller recommended Multi-word DMA transfer cycle time. This field defines, in
nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a multiple
sector READ DMA or WRITE DMA command for any location on the media under nominal conditions. If a host
runs at a faster cycle rate by operating at a cycle time of less than this value, the NAND Controller may negate
DMARQ for flow control. The rate at which DMARQ is negated could result in reduced throughput despite the
faster cycle rate. Transfer at this rate does not ensure that flow control will not be used, but implies that higher
performance may result. NAND Controller supports Multi-word DMA Mode-2, so this field is set to 120ns.
Note: NAND Controller is capable of supporting Multi-word DMA Mode-2 cycle time of 80ns
(0050H). Contact SST sales for more details.
相關(guān)PDF資料
PDF描述
SST55VD020-60-C-MVWE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA85
SST55VD020-60-I-TQWE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP100
SST55VD020-60-C-MVWE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA85
SST55VD020-60-I-TQWE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP100
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