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參數(shù)資料
| 型號： | SST55LD040M-133-C-BZJE |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA145 |
| 封裝： | 12 X 12 MM, 1.07 MM HEIGHT, ROHS COMPLIANT, TFBGA-145 |
| 文件頁數(shù)： | 23/39頁 |
| 文件大小： | 589K |
| 代理商： | SST55LD040M-133-C-BZJE |
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Advance Information
NAND Controller
SST55LD040M
2010 Silicon Storage Technology, Inc.
S71408-01-000
04/10
3
GENERAL DESCRIPTION
The SST55LD040M NAND Controller contains a micro-
controller and a flash file system integrated in a TFBGA
package. Refer to Figure 1 for the NAND Controller block
diagram. The controller interfaces with the host system
allowing data to be written to and read from the flash
media.
Performance-optimized NAND Controller
The heart of the flash drive is the NAND Controller which
translates standard ATA signals into flash media data and
control signals. The following components contribute to the
NAND Controller’s operation.
Microcontroller Unit (MCU)
The 32 bit RISC MCU transfers the ATA/IDE commands
into required flash media operations.
Power Management Unit (PMU)
The power management unit controls the power consump-
tion of the NAND Controller. The PMU dramatically
reduces the power consumption of the NAND Controller by
putting the part of the circuitry that is not in operation into
sleep mode. The PMU is designed so that it has zero
wake-up latency when using the internal clock.
SRAM Buffer
A contributor to the NAND Controller performance is an
SRAM buffer. The buffer optimizes the host’s data transfer
to and from the flash media.
Flash File System
The flash file system is an integral part of the NAND Con-
troller. It contains MCU firmware that performs the following
tasks:
1. Translates host side signals into flash media
writes and reads.
2. Provides advanced flash media wear leveling to
spread the flash writes across the entire memory
address space to increase the longevity of flash
media.
3. Keeps track of data file structures.
4. Manages system security for the selected protec-
tion zones.
5. Stores the data in Flash media upon completion of
a Write command. The NAND Controller does not
do Post-Write operations, except for when the
Write cache is enabled by the Host command.
Serial Communication Interface (SCI)
The Serial Communication Interface (SCI) is designed to
provide trace information during debugging processes.To
aid in validation, always provide the SCI access to PCB
design.
Media Interface Block (MIB)
The SST55LD040M contains two Media Interface Blocks,
MIB0 and MIB1. The MIB work independently to transfer
data to and from the NAND Flash media. Each MIB con-
trols two 8-bit channels.
Each Media Interface Block has three functions: DMA,
ECC, and Programmable Multi-tasking NAND Interface.
Programmable, Multi-tasking NAND Interface The
multi-tasking interface enables fast, sustained write perfor-
mance by allowing multiple Read, Program, and Erase
operations to multiple flash media devices. The ease with
which the NAND interface can be programmed enables the
quick support of new NAND devices.
Internal Direct Memory Access (DMA) The
NAND
Controller uses internal DMA allowing instant data transfer
from buffer to flash media. This implementation eliminates
microcontroller overhead associated with the traditional,
firmware-based approach, thereby increasing the data
transfer rate.
Error Correction Code (ECC) The
SST55LD040M
utilizes 24-bit, BCH Error detection Code (EDC) and
Error Correction Code (ECC) algorithms. The ECC
engine can provide, depending on settings, 6 or 12 bits of
ECC for each 512-Byte block of data, and 12 or 24 bits of
ECC for each 1KByte of data.
The ECC encoding and decoding operations occur during
the data transfer.
External Clock The SST55LD040M supports an exter-
nal clock interface (XCLKI) that is enabled, or disabled, by
the external clock enable (XCLKEN) input signal. With a
4.7K
Ω pull-down resistor connected to the XCLKEN pin,
and a 6.0 MHz external oscillator or clock source present at
the XCLKI input pin, the SST55LD040M uses the external
oscillator as the internal clock reference.
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| SST55VD020-60-C-MVWE | 功能描述:閃存 ATA Media 60MHz 3.3V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST55VD020-60-C-TQWE | 功能描述:閃存 ATA Media 60MHz 2.7V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST55VD020-60-I-MVWE | 功能描述:總線收發(fā)器 ATA Media 60MHz 3.3V Industrial RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SST55VD020-60-I-TQWE | 功能描述:閃存 ATA Media 60MHz 3.3V Industrial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST55VD020-60-I-TQWE-TM024 | 功能描述:閃存 ATA Media 60MHz 3.3V Industrial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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