參數(shù)資料
型號(hào): SST55LC100M-45-C-BWE
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: 9 X 9 MM, ROHS COMPLIANT, TFBGA-84
文件頁(yè)數(shù): 62/75頁(yè)
文件大小: 1040K
代理商: SST55LC100M-45-C-BWE
Advance Information
CompactFlash Card Controller
SST55LC100M
2006 Silicon Storage Technology, Inc.
S71316-00-000
3/06
65
10.2.6 I/O Output (Write) Timing Specification
Note: The maximum load on -INPACK, and IOIS16# is 1 LSTTL with 50pF total load.
FIGURE
10-7: I/O Write Timing Diagram
TABLE 10-12:I/O Write Timing
Item
Symbol
IEEE Symbol
Min1
1. All AC specifications are guaranteed by design.
Max1
Units
Data Setup before IOWR
tsu(IOWR)
tDVIWH
60
ns
Data Hold following IOWR
th(IOWR)
tlWHDX
30
ns
IOWR Width Time
tw(IOWR)
tlWLIWH
165
ns
Address Setup before IOWR
tsuA(IOWR)
tAVIWL
70
ns
Address Hold following IOWR
thA(IOWR)
tlWHAX
20
ns
CE Setup before IOWR
tsuCE(IOWR)
tELIWL
5
ns
CE Hold following IOWR
thCE(IOWR)
tlWHEH
20
ns
REG Setup before IOWR
tsuREG(IOWR)
tRGLIWL
5
ns
REG Hold following IOWR
thREG(IOWR)
tlWHRGH
0
ns
IOIS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
ns
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
ns
T10-12.0 1316
1316 F08.0
REG#
tdrIOIS16(ADR)
thA(IOWR)
thREG(IOWR)
thCE(IOWR)
tw(IOWR)
tdfIOIS16(ADR)
tsu(IOWR)
th(IOWR)
DIN Valid
tsuA(IOWR)
tsuREG(IOWR)
tsuCE(IOWR)
An
CE#
IOWR#
IOIS16#
DIN
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