參數(shù)資料
型號: SST55LC100M-45-C-BWE
元件分類: 存儲控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: 9 X 9 MM, ROHS COMPLIANT, TFBGA-84
文件頁數(shù): 13/75頁
文件大小: 1040K
代理商: SST55LC100M-45-C-BWE
20
Advance Information
CompactFlash Card Controller
SST55LC100M
2006 Silicon Storage Technology, Inc.
S71316-00-000
3/06
Changed
Indicates that one or both of the Pin Replacement register CRdy or CWProt bits are set
to one (1). When the Changed bit is set, Pin 46 (STSCHG#) is held low if the SigChg bit
is a One (1) and the CompactFlash card is configured for the I/O interface.
SigChg
This bit is set and reset by the host to enable and disable a state-change “signal” from
the Status register, the Changed bit control pin 46 the Changed Status signal. If no state
change signal is desired, this bit should be set to zero (0) and pin 46 (STSCHG#) signal
will be held high while the CompactFlash card is configured for I/O.
IOis8
The host sets this bit to a one (1) if the CompactFlash card is to be configured in an 8-bit
I/O mode. The CompactFlash card is always configured for both 8- and 16-bit I/O, so this
bit is ignored.
XE#:
This bit has value 0 and is not writable.
Audio:
This bit should always be zero for CompactFlash cards.
PwrDwn
This bit indicates whether the host requests the CompactFlash card to be in the power
saving or active mode. When the bit is one (1), the CompactFlash card enters a power
down mode. When zero (0), the host is requesting the CompactFlash card to enter the
active mode. The PCMCIA Ready value becomes BUSY when this bit is changed.
Ready will not become ready until the power state requested has been entered. The
CompactFlash card automatically powers down when it is idle and powers back up when
it receives a command.
Int
This bit represents the internal state of the interrupt request. This value is available
whether or not I/O interface has been configured. This signal remains true until the
condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEn bit in the Device Control register, this bit is a zero (0).
TABLE
8-4: Card Configurations
Conf5
Conf4
Conf3
Conf2
Conf1
Conf0
Disk Card Mode
0
Memory Mapped
0
1
I/O Mapped, any 16 Byte system
decoded boundary
0
1
0
I/O Mapped, 1F0H-1F7H/3F6H-3F7H
0
1
I/O Mapped, 170H-177H/376H-377H
T8-4.0 1316
TABLE
8-5: Card Configuration and Status Register Organization
Operation
D7
D6
D5D4
D3D2D1D0
Read
Changed
SigChg
IOis8
XE#
Audio
PwrDwn
Int
0
Write
0
SigChg
IOis8
XE#
Audio
PwrDwn
0
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