參數(shù)資料
型號: SST55LC100M-45-C-BWE
元件分類: 存儲控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: 9 X 9 MM, ROHS COMPLIANT, TFBGA-84
文件頁數(shù): 24/75頁
文件大小: 1040K
代理商: SST55LC100M-45-C-BWE
30
Advance Information
CompactFlash Card Controller
SST55LC100M
2006 Silicon Storage Technology, Inc.
S71316-00-000
3/06
9.1.5.9 Status & Alternate Status Registers (Address 1F7H[177H]&3F6H[376H]; Offsets 7 & E)
These registers return the CompactFlash card status when read by the host. Reading the Status register does
clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are
described as follows:
Symbol
Function
Bit 7 (BUSY) The busy bit is set when the CompactFlash card has access to the command buffer and
registers and the host is locked out from accessing the command register and buffer. No
other bits in this register are valid when this bit is set to a 1.
Bit 6 (RDY)
RDY indicates whether the device is capable of performing CompactFlash card
operations. This bit is cleared at power up and remains cleared until the CompactFlash
card is ready to accept a command.
Bit 5 (DWF)
This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC)
This bit is set when the CompactFlash card is ready.
Bit 3 (DRQ)
The Data Request is set when the CompactFlash card requires that information be
transferred either to or from the host through the Data register.
Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX)
This bit is always set to 0.
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error. It is required that
the host retry any media access command (such as Read Sectors and Write Sectors)
that ends with an error condition.
9.1.5.10 Device Control Register (Address - 3F6H[376H]; Offset E)
This register is used to control the CompactFlash card interrupt request and to issue an ATA soft reset to the card.
This register can be written even if the device is BUSY. The bits are defined as follows:
Symbol
Function
Bits 7-3
These bits are ignored by the CompactFlash card.
Bit 2 (SW Rst) This bit is set to 1 in order to force the CompactFlash card to perform an ATA Disk
controller Soft Reset operation. This does not change the PCMCIA Card Configuration
registers (Sections 8.2 to 8.4) as a hardware reset does. The card remains in Reset until
this bit is reset to ‘0.’
Bit1(-IEn)
The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts
from the CompactFlash card are disabled. This bit also controls the Int bit in the
Configuration and Status register. This bit is set to 0 at Power-on and Reset.
Bit0
This bit is ignored by the CompactFlash card.
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
1000 0000b
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
XXXXX
SW Rst
-IEn
0
0000 1000b
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