參數(shù)資料
型號(hào)： SPC5604PGF0MLQ6
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 83/104頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 512KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝： 60
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 64MHz
連通性： CAN，F(xiàn)lexRay，LIN，SPI，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 108
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 64K x 8
RAM 容量： 40K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 30x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 144-LQFP
包裝： 托盤
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
8
1.5.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting
that slave port will be stalled until the higher priority master completes its transactions. Requesting masters will be treated with
equal priority and will be granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted
access.
The crossbar provides the following features:
4 master ports:
— e200z0 core complex Instruction port
— e200z0 core complex Load/Store Data port
—eDMA
—FlexRay
3 slave ports:
— Flash memory (code flash and data flash)
—SRAM
— Peripheral bridge
32-bit internal address, 32-bit internal data paths
Fixed Priority Arbitration based on Port Master
Temporary dynamic priority elevation of masters
1.5.3
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is utilized to minimize the overall block size.
The eDMA module provides the following features:
16 channels support independent 8, 16 or 32-bit single value or block transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to either post-increment or to remain constant
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU
Programmable DMA channel multiplexer for assignment of any DMA source to any available DMA channel with as
many as 30 request sources
eDMA abort operation through software
1.5.4
Flash memory
The MPC5604P provides as much as 576 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM)
can be used for instruction and/or data storage. The flash memory module interfaces the system bus to a dedicated flash memory
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