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參數(shù)資料
型號(hào): SPC5604PGF0MLQ6
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 81/104頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 144LQFP
標(biāo)準(zhǔn)包裝: 60
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,F(xiàn)lexRay,LIN,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 108
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64K x 8
RAM 容量: 40K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 30x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 144-LQFP
包裝: 托盤
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
78
3.17.2
IEEE 1149.1 interface timing
ttr
CC D Output transition time
output pin3
MEDIUM configuration
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
ns
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
40
WFRST SR P RESET input filtered
pulse
——
40
ns
WNFRST SR P RESET input not filtered
pulse
—500
ns
tPOR CC D Maximum delay before
internal reset is released
after all VDD_HV reach
nominal supply
Monotonic VDD_HV supply ramp
1
ms
|IWPU| CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
150
A
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
150
VDD = 5.0 V ± 10%, PAD3V5V = 14
10
250
1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
device reference manual).
3 CL includes device and package capacitance (CPKG <5pF).
4 The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 37. JTAG pin AC electrical characteristics
No.
Symbol
C
Parameter
Conditions
Value
Unit
Min Max
1tJCYC
CC
D TCK cycle time
100
ns
2tJDC
CC
D TCK clock pulse width (measured at VDD_HV_IOx/2)
40
60
ns
3tTCKRISE
CC
D TCK rise and fall times (40% – 70%)
3
ns
4tTMSS, tTDIS CC D TMS, TDI data setup time
5
ns
Table 36. RESET electrical characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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