參數(shù)資料
型號: SPAKDSP321VL275
廠商: Freescale Semiconductor
文件頁數(shù): 41/84頁
文件大小: 0K
描述: IC DSP 24BIT 275MHZ 196-MAPBGA
標準包裝: 126
系列: DSP56K/Symphony
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 275MHz
非易失內存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應商設備封裝: 196-MAPBGA(15x15)
包裝: 托盤
DSP56321 Technical Data, Rev. 11
2-26
Freescale Semiconductor
Specifications
2.4.9
Timer Timing
Figure 2-25.
ESSI Receiver Timing
Table 2-13.
Timer Timings
No.
Characteristics
Expression
200 MHz
220 MHz
240 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
480
TIO Low
2
× TC + 2.0
12.0
11.1
10.3
9.27
ns
481
TIO High
2
× TC + 2.0
12.0
11.1
10.3
9.27
ns
486
Synchronous delay time from Timer input
rising edge to the external memory
address out valid caused by the first
interrupt instruction execution
10.25
× T
C + 10.0
61.2
5
—56.6
4
—52.7
4
—47.2
7
—ns
Notes:
1.
VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
2.
The maximum frequency of pulses generated by a timer will be defined after device characterization is completed.
3.
In the timing diagrams below, TIO is drawn using the rising edge as the reference. TIO polarity is programmable in the Timer
Control/Status Register (TCSR). Refer to the
DSP56321 Reference Manual for details.
Last Bit
First Bit
430
432
433
437
438
440
439
443
441
442
443
445
444
431
434
RXC
(Input/
Output)
FSR (Bit)
Out
FSR
(Word)
Out
Data In
FSR (Bit)
In
FSR
(Word)
In
Flags In
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