參數(shù)資料
型號: SPAKDSP321VL275
廠商: Freescale Semiconductor
文件頁數(shù): 27/84頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 275MHZ 196-MAPBGA
標準包裝: 126
系列: DSP56K/Symphony
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 275MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤
AC Electrical Characteristics
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-13
2.4.5.2 Asynchronous Bus Arbitration Timings
Figure 2-11.
SRAM Write Access
Table 2-9.
Asynchronous Bus Timings
No.
Characteristics
Expression
200 MHz
220 MHz
240 MHz
275 Mhz
Uni
t
Min
Max
Min
Max
Min
Max
Min
Max
250
BB assertion window from BG input
deassertion.
2.5
× Tc + 5
17.5
16.4
15.4
14.1
ns
251
Delay from BB assertion to BG assertion
2
× Tc + 5
15
14.1
13.3
12.27
ns
Notes:
1.
Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.
2.
To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300
devices (on the same bus), as shown in Figure 2-12, where BG1 is the BG signal for one DSP56300 device while BG2 is the
BG signal for a second DSP56300 device.
A[0–17]
WR
RD
Data
Out
D[0–23]
AA[0–3]
100
102
101
107
114
108
109
103
TA
118
119
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
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