參數(shù)資料
型號: SPAKDSP311VL150
廠商: Freescale Semiconductor
文件頁數(shù): 34/96頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 150MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝: 2
系列: DSP56K/Symphony
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時鐘速率: 150MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 384kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤
DSP56311 Technical Data, Rev. 8
iv
Freescale Semiconductor
Target Applications
DSP56311 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
DSP resource boards
High-speed modem banks
IP telephony
Product Documentation
The documents listed in Table 2 are required for a complete description of the DSP56311 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
External Memory
Expansion
Data memory expansion to two 256 K
× 24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K
× 24-bit words memory space using the standard external
address lines
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Internal DRAM controller for glueless interface to dynamic random access memory (DRAMs) up to 100
MHz operating frequency
Power Dissipation
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Packaging
Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Table 2. DSP56311 Documentation
Name
Description
Order Number
DSP56311
User’s Manual
Detailed functional description of the DSP56311 memory configuration,
operation, and register programming
DSP56311UM
DSP56300 Family
Manual
Detailed description of the DSP56300 family processor core and instruction set
DSP56300FM
Application Notes
Documents describing specific applications or optimized device operation
including code examples
See the DSP56311 product website
Table 1. DSP56311 Features (Continued)
Feature
Description
相關(guān)PDF資料
PDF描述
VE-24T-CW-F1 CONVERTER MOD DC/DC 6.5V 100W
VE-24P-CW-F3 CONVERTER MOD DC/DC 13.8V 100W
VE-2TR-CW-F4 CONVERTER MOD DC/DC 7.5V 100W
VI-25B-CY-S CONVERTER MOD DC/DC 95V 50W
TPSD156M025R0100 CAP TANT 15UF 25V 20% 2917
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