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參數(shù)資料
| 型號： | SPAK56F807VF80 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 80 MHz, OTHER DSP, PBGA160 |
| 封裝： | MOLD ARRAY PROCESS, BGA-160 |
| 文件頁數(shù)： | 3/48頁 |
| 文件大?。?/td> | 853K |
| 代理商： | SPAK56F807VF80 |
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GPIO Signals
MOTOROLA
DSP56F807 Preliminary Technical Data
11
2.6 GPIO Signals
2.7 Pulse Width Modulator (PWM) Signals
1
RESET
Input
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the DSP is initialized and
placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in a
debugging environment when a hardware DSP reset is
required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
1
EXTBOOT
Input
External Boot—This input is tied to VDD to force device to
boot from off-chip memory. Otherwise, it is tied to VSS.
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
8
GPIOB0-
GPIOB7
Input
or
Output
Input
Port B GPIO—These eight pins are dedicated General
Purpose I/O (GPIO) pins that can individually be
programmed as input or output pins.
After reset, the default state is GPIO input.
6
GPIOD0-
GPIOD5
Input
or
Output
Input
Port D GPIO—These six pins are dedicated GPIO pins that
can individually be programmed as an input or output pins.
After reset, the default state is GPIO input.
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0-5
Output
Tri- stated
PWMA0-5— Six PWMA output pins.
3
ISA0-2
Input
ISA0-2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
4
FAULTA0-3
Input
FAULTA0-3— These Fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions
originate off-chip.
Table 10. Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
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